In reply to Sanjin_Arsenovic:
You should never have this situation as it creates a infinite loop of references. You will end up with A → b1 → a1 → b1 → a1 → … ad infinitum.
However, if you were to implement this, it would have to be within a single package. SystemVerilog requires all classes to be fully defined within a package, either by implementation or import. A typedef does not meet this requirement.