Topics tagged include

Topic	Replies	Views	Activity
Not a valid compilation unit/global item: 'module/udp instance' [SystemVerilog] SystemVerilog SystemVerilog , include , UVM-system-verilog	1	3228	June 8, 2021
Is that legal? variable_name = `include(init_value.sv) SystemVerilog SystemVerilog , include	1	586	June 8, 2021
SystemVerilog include import SystemVerilog SystemVerilog , UVM , Package , import , include	4	2826	April 18, 2018
Compilation error cause by testbench package UVM UVM , Package , include , NPITEM , Compilation-Error	4	5548	September 23, 2015
`include vs import UVM UVM , import , include	4	10752	February 26, 2014