Not a valid compilation unit/global item: 'module/udp instance' [SystemVerilog]

SystemVerilog
, ,
1

In UVM Testbench i have many checker modules instantiated in top module. I want to combine them in one file and include that file in top module. Those modules are instantiated between `ifdef .
But getting this error. Not a valid compilation unit/global item: ‘module/udp instance’ [SystemVerilog].

module top
ifdef assert_en include “assert.sv”
`endif
endmodule

Contents of asset.sv file:

checker u_checker (.a(a),.b(b)…);

Is this possible to do?

2

In reply to Vaishali Ahuja 1010:

It would help to provide the full error message including line number it is pointing to, and the smallest amount of code that reproduces your issue.

Also, you are missing a semicolon at the end of your first line.