Is that legal? variable_name = `include(init_value.sv)

SystemVerilog
,
1

Hi,

I want to init a queue with included file.
and I want to control the queue’s name out of the included file:

_init_value.sv:
_



'{1, 2, 3};

_main.sv:
_



int myvar[$};

myvar = `include(init_value.sv)
$display("%d", myvar[0])

Is the “include” line legal?
I didn’t find anything like that online… but it works… I’m looking for some “formal” proof.

edit:

I ment:



myvar = `include "init_value.sv"
2

In reply to uriyam:

From section 22.4 of the LRM, the `include directive has the format of:

include "filename" include <filename>

There is no format with parenthesis that is valid.

The LRM also specifies:
“Only white space or a comment may appear on the same line as the `include compiler directive”
So you will need to do something like:


module testbench();
  int myvar[$];
 
  initial begin
    myvar =
`include "init_value.sv"
    $display("%d", myvar[0]);
  end
endmodule