Package Variable imported in multiple modules

SystemVerilog
,
1

Please correct me if this is wrong, but can the same variable declared in a package be shared by multiple modules which import that package?


package p;
  int x;
endpackage

module m1;
  import p::*;
  initial begin
    x = 5;
  end
endmodule

module m2;
  import p::*;
  initial begin
     #10;
     x += 3;
  end
endmodule

In the above example is the final value of p::x=8?

2

In reply to astoddard:
Yes, it can be shared by multiple modules and the final updated value of the x will be 8.

PS: For readability purpose, it’s advisable to use the variable with package name and scope resolution operator, like p::x instead of x.

3

In reply to bdreku:

Note that although SystemVerilog allows global shared variables in a package, having two processes concurrently accessing to them is not a generally good programming practice. Better to use a mailbox or some combination of semaphores and queues (which can sill be declared inside a common package).

4

In reply to dave_59:

Yes that’s for sure Dave-- I was just wanting to confirm that multiple modules could indeed access the same variable if they both imported the package.