PACKAGE doubt

SystemVerilog
,
1

Hello friends, sorry to ask very stupid question.
I am very new to this verification field.

I am posting my code below.
I have packet class, where i have defined all my FIELDS.
I have generator class, where those fields are being randomnized.
I have my driver class, where the fields which are randomized by generator class, are retrieved from mailbox.

But i am getting a list of error, saying that.
“Typedef ‘generator_t’ multiply defined.”

Can you please provide appropriate working solution for this.
I have referred to some documents, they asked to use PACKAGE CONCEPT.
But practically i didnt understood what they are trying to say in PACKAGE CONCEPT.
Please elabrote.

Thank you.

PACKET CLASS:

typedef enum bit [1:0] {IDLE,BUSY,NONSEQ,SEQ}ttype;
typedef enum bit [2:0] {BYTE,HALFWORD,WORD,DOUBLEWORD,
                        WORD4,WORD8,BIT_512,
                        BIT_1024} hsize;
typedef enum bit [2:0] {SINGLE,INCR,WRAP4,INCR4,
                        WRAP8,INCR8,WRAP16,INCR16} hburst;
typedef enum bit [3:0] {ONE,TWO,THREE,FOUR} hprot;


class packet;

rand bit [31:0] add;
rand bit [31:0] hwdata;
rand bit hwrite;
rand bit hmastlock;
rand ttype type1; // VARIABLE for ENUM
rand hsize size; // VARIABLE for ENUM
rand hburst burst; // VARIABLE for ENUM
rand hprot prot; //VAIRABLE FOR ENUM

constraint c1 {add dist{[0:1048]:=25,
                                [1049:2096]:=25,
                                [2097:3144]:=25,
                                [3145:4196]:=25};}; 
constraint c2 {prot > 2;prot<4;};


endclass: packet
--------------------------
GENERATOR CLASS

`include"packet_class.sv"

class generator_t;

packet p2rand;
packet p2send;

static int id;

mailbox #(packet) gen2drv;

function new();
this.p2rand=new();
this.gen2drv=new();
endfunction

function void disp123();
  
  $display("\nSTART OF FIELDS DETIALS %0d\n",id);
  $display("Address : %h",p2rand.add);
  $display("Data : %h",p2rand.hwdata);
  $display("HWRITE : %b",p2rand.hwrite);
  $display("MASTER LOCK : %b",p2rand.hmastlock);
  $display("transfer type : %s (%b)",p2rand.type1,p2rand.type1);
  $display("transfer size : %s (%b)",p2rand.size,p2rand.size);
  $display("burst transfer type : %s (%b)",p2rand.burst,p2rans.burst);
  $display("Protection Level : %s (%b)",p2rand.prot,p2rand.prot);
  $display("\nEND OF FIELDS DETIALS %0d\n",id);
  
  $display("%p",p2rand);
  $display("%p",p2send);
endfunction

function dorando();
if(p2rand.randomize())
id++;
p2send = new p2rand;
this.disp123();
endfunction

task mb_gen2dri();
this.gen2drv=new();
//this.p2dri=new();
begin 
gen2drv.put(p2send);
end
p2rand.randomize();
endtask

endclass: generator_t
----------------------------
DRIVER CLASS

//`include"packet_class.sv"
`include"generator_class.sv"

class driver;

packet p2recv;
//packet p2intf;

mailbox #(packet) gen2dri;

function new(mailbox #(packet) gen2drv);
this.gen2drv = gen2drv;
endfunction

function void disp_drv();
$display("%p recieved packet",p2recv);
endfunction

virtual task doit();
begin
gen2drv.get(p2recv);
end
endtask

endclass
------------------------
PROGRAM BLOCK

`include"generator_class.sv"
`include"driver_class.sv"

program test1();

generator_t gen=new();
driver drv;

initial begin
drv = new(gen.gen2drv);
repeat(5)
begin


gen.dorando();
gen.mb_gen2dri();
drv.doit();
drv.disp_drv();
end
end
endprogram
2

You should read this article about the use of packages versus include files.

3

You have included generator_class.sv twice; once in the program file and once in the driver class. Both these are also defined in the same root scope. Hence you are seeing multiple definitions.

As Dave (dave_59) suggest you need to use packages. You would need to define generator class inside a package and import the package in the scope where you need it. This will eliminate your symbol clashes.

package MyPackage; 

   class generator_t; 
    ... 
    ...
   endclass 

endpackage

Import using

import MyPackage::*;

in any scope;

Refer to Section 26 of the 1800-2012 SystemVerilog reference manual for detailed instructions.

4

In reply to logie:

I have a similar issue and when I follow your solution, I get another error :
–Compiling package eth_env_pkg
** Error: ** while parsing file included at /home/user1/Vansh/1118asrt/eth_top.sv(6)
** while parsing file included at eth_env.sv(8)
** at eth_pkt_pkg.sv(1): near “package”: syntax error, unexpected package, expecting class

eth_top.sv(6): include "eth_env.sv" // Contains Top module and imports required files and packages eth_env.sv(8): include “eth_pkt_pkg.sv” // Contains a package “eth_env_pkg” which contains the class “eth_env_c”
eth_pkt_pkg.sv(1): `include “eth_pkt.sv” // Contains just this line, eth_pkt.sv contains definition of the class “eth_pkt”
Same error even if I try declaring the class inside the package in the same file too.

What am I doing wrong?
Why does it expect a class when I want to define a package?
Even if I define the class inside the package, then also it expects a class. Why is it so?

5

In reply to Vanshlata_cdac:
Could you please share the snippets of your package class (eth_pkt_pkg.sv) and an included file list of eth_env.sv.

6

In reply to bdreku:

contents of eth_pkt_pkg.sv
package eth_pkt_pkg;
`include “eth_pkt.sv”
endpackage:eth_pkt_pkg

contents of eth_pkt.sv
class eth_pkt;
rand bit [31:0] pkt_da;
rand bit [31:0] pkt_sa;
.
.
.
.
endclass:eth_pkt

contents of eth_env.sv
package eth_env_pkg;
include "eth_pkt_pkg.sv" include “eth_pkgn.sv”
include "eth_drvr.sv" include “eth_mntr.sv”
`include “eth_chkr.sv”
import eth_pkt_pkg::eth_pkt;

class eth_env_c;
.
.
.
.
endclass:eth_env_c

contents of eth_top.sv
include "eth_env.sv" include “eth_if.sv”
import eth_env_pkg::*;
module eth_top();
.
.
.
endmodule:eth_top

7

In reply to Vanshlata_cdac:

[i]
contents of eth_env.sv
package eth_env_pkg;
`include “eth_pkt_pkg.sv”

It seems that you have declared the package at the first line and included the package file at the second line of the eth_env.sv file.
In SV, package inside a package is not allowed.

P.S.: Please use a proper code format while inserting a code in this forum. It would make a code readable.

8

In reply to Vanshlata_cdac:

As the reply from bdreku states, you shouldn’t `include any package inside of another package.

Each package .sv file should be compiled independently into a library. In turn, if you need to reference that package from another package or environment, then you should import it.

Example:

eth_pkt.sv


class eth_pkt;
rand bit [31:0] pkt_da;
rand bit [31:0] pkt_sa;
.
.
.
.
endclass:eth_pkt

contents of eth_pkt_pkg.sv


package eth_pkt_pkg;
`include "eth_pkt.sv"
endpackage:eth_pkt_pkg

contents of eth_env.sv


package eth_env_pkg;
import eth_pkt_pkg::eth_pkt;
`include "eth_pkgn.sv"
`include "eth_drvr.sv"
`include "eth_mntr.sv"
`include "eth_chkr.sv"

class eth_env_c;
.
.
.
.
endclass:eth_env_c
endpackage:eth_env_pkg

contents of eth_top.sv


import eth_env_pkg::*;
`include "eth_if.sv"

module eth_top();

Also, if you are using UVM, you should have import uvm_pkg::*; and `include “uvm_macros.svh” as the first two lines of every package.

9

In reply to cgales:

Thanks a lot bdreku and cgales for such a quick response !!

Can you also tell me how to insert codes with proper format(I mean indentation and colour etc) here instead of typing?

10

In reply to Vanshlata_cdac:
Hi Vanshlata,

Just write a code, select the code you want to format and use the code menu from a toolbar (see the last menu at the top of the text box)and select the respective code patterns from VHDL, Verilog or SystemVerilog.

Then use Preview button to ensure that your code is formatted properly.

11

In reply to bdreku:

Oh, this is so cool !!

Thanks a lot people :)