PACKAGE doubt

SystemVerilog
,
3

You have included generator_class.sv twice; once in the program file and once in the driver class. Both these are also defined in the same root scope. Hence you are seeing multiple definitions.

As Dave (dave_59) suggest you need to use packages. You would need to define generator class inside a package and import the package in the scope where you need it. This will eliminate your symbol clashes.

package MyPackage; 

   class generator_t; 
    ... 
    ...
   endclass 

endpackage

Import using

import MyPackage::*;

in any scope;

Refer to Section 26 of the 1800-2012 SystemVerilog reference manual for detailed instructions.