Including same file in 2 different packages

SystemVerilog
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  1. In my $WRK/tb/env I have defined v_seqr and env components and env_pkg which includes these 2 files
class v_seqr extends uvm_sequencer;
  `uvm_component_utils( v_seqr )
   .....
endclass

class env extends uvm_component;
  `uvm_component_utils( env )
    v_seqr  vseqr_h;
    //  In  build_phase()
    vseqr_h = v_seqr::type_id::create("vseqr_h",this);
    .....
endclass

package env_pkg;
  `include "v_seqr.sv"
  `include "env.sv"
endpackage
  1. In my $WRK/tb/seq I have defined base_seq class and seq_pkg which includes it as well as v_seqr
class base_seq extends uvm_sequence#(user_seq_item);
  `uvm_object_utils(base_seq)
  `uvm_declare_p_sequencer( v_seqr )
   ....
endclass

package seq_pkg;
   ....
   import env_pkg::*;  // Internally does  `include "v_seqr.sv"
  `include "v_seqr.sv"
  `include "base_seq.sv"
endpackage

Note that env-pkg also includes file “v_seqr.sv”

Q1] Shouldn’t there be a compilation error since the v_seqr is being compiled twice ?
i.e wouldn’t seq_pkg be equivalent to

 package seq_pkg;
  // On expanding the import env_pkg::*; 
  `include "v_seqr.sv"
  `include "env.sv"

  `include "v_seqr.sv"
  `include "base_seq.sv"
endpackage

Q2] Does class ‘v_seqr’ class exist in 2 different scopes ( env_pkg and seq_pkg ) ?

2

See: SystemVerilog Coding Guidelines: Package import versus `include - Verification Horizons