Accessing hierarichal nets inside system verilog packages

SystemVerilog
,
1

In the paper "Abstract BFM", in Figure 1, the authors show the system Verilog package access hierarichal nets.

package stimulus_pkg;
  class Stimgen;
    task run();
      repeat(10) begin
        #5 testbench_Top.R = 1'b0;
        #5 testbench_Top.R = 1'b1;
      end
    endtask
  endclass
endpackage

As per my understanding, this is wrong. I checked in EdaPlayground and got the error that I expected. Is something I am missing?

2

Hierarchical references are not allowed from a package by the LRM. I didn’t read the paper, but either the example is incorrect or it is out-of-date.

3

In reply to sanjeevs:

I was the co-author of that paper. I believe the example was intended to show what you would likely want to do at first glance, and why it would you eventually not want it to work. I don’t believe hierarchical references were ever allowed from a package.