So there is transaction which has rand variable.
class txn;
bit en;
bit an;
bit d,c,d,e;
rand bit wr;
rand bit[6:0] dyn_addr;
constraint one { soft dyn_addr==50;}
constraint two { soft wr == 1; }
endclass
it is soft constrained.
A sequnece dyn_addr_seq is created.
class dyn_addr extends uvm_sequence;
txn.en=1;
txn.an=1;
start_item(txn);
assert(txn.randomize() with { txn.wr == 0;}}
finish_item(txn);
endclass
this sequence is printing dyn_addr;
similarly like this 3 other sequences are being created and txn is randomized in all 3 sequences.Some other variables of txn are assigned and randomized not wr.
In a new sequence consided write_data sequence extended by virtual sequence all these 4 sequences are being started.Purpose of this sequence is to write data in dynamic address.All 4 sequences are subsequences in this.
I’m extending ext_wrt_seq from write_data_seq and trying to modify txn dynamic address here.
assert(dy_wr.tx.randomize() with {
dy_wr.txn.dyn_addr inside {[7'h60:7'h67]};
dy_wr.txn.wr == 0;
});
super.body();
so that when run dyn_addr should come between 60:67 is this the right approach? when simulation is run i’m getting data in loaction 60:67 sometimes and some times in other location. Is it because of txn gets re randomized in all 4 sub sequences when super.body() is called. How to make sure that dy_addr should be fixed not be able to change when txn is randomized.
tried using txn.rand_mode(0) but whole txn randomization is getting stopped. I just need dyn_addr inside 60:67 and once it is randomized it should be fixed.