TLM PORTS how it giving the access of other class TASK with other class handle

UVM
1

In the diagram below, we make a connection between DRIVER and GENERATOR.

In DRIVER we declared a handle of uvm_blocking_port #(xtn) get_port and in GENERATOR class we declared uvm_blocking_get_imp #(xtn,generator) get_imp ; and also there is a method (task) of get in generator class.

Now if we observe that in driver class we used a handle of uvm_blocking_port class of get_port how we are getting the GET method which is there in Generator class by using other class handle.

explain me how internally it is giving access to driver class GET task

When the driver calls get_port.get() how does this call reach the get() task in the generator, even though get_port is of type uvm_blocking_get_port (a different class)? @dave_59 @chr_sue

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2

The UVM is using an “Adaptor Design Pattern” which essentially creates a series of procedure call wrappers through an intermediate adaptor class. The uvm_blocking_get_port has a get() method that calls the get() method of the uvm_blocking_get_imp. The uvm_blocking_get_imp::get() calls ahb_generator::get(). I’ve simplified it here, but you can do a search for that design pattern as well as UVM TLM connections.