Reset code in uvm

UVM
,
1

HI All,

What could be the best approach to have reset code in uvm_driver


//APPROACH_1 : Having separate task for reset inside driver
virtual task run_phase(uvm_phase phase);
drive_reset();

forever begin
seq_item_port.get_next_item(req);
drive_to_dut();
seq_item_port.item_done();
end

endtask


task drive_reset;
vif.reset=1;
repeat (2) @(posedge vif.clock);
vif.reset=0;
endtask

//APPROACH_2 : Using built_in phase (reset_phase) in driver

virtual task reset_phase(uvm_phase phase);
phase.raise_objection(this);
vif.reset=1;
repeat (2) @(posedge vif.clock);
vif.reset=0;
phase.drop_objection(this);
endtask


//APPROACH_3 : writing reset code in tb_top (testbench top) file
module tb_top;

initial begin
reset=1;
#5 reset=0;
end

endmodule


//APPROACH_4 : Having separate reset sequence

class my_seq_item extends uvm_sequence_item;
`uvm_object.....

rand logic reset;
.......
endclass

class my_base_seqeunce extends uvm_sequence;

task body;
reset_pkt = my_seq_item::type_id::create("reset_pkt");
start_item(reset_pkt);
reset_pkt.randomize() with {reset==1};
finish_item(reset_pkt);
endtask

endclass

//now, we can use this my_base_sequence before we start the actual test_sequence inside uvm_test


//Actual Question : Which is the best or recommended approach to have reset code while verifying a design. 
Any limitations with these, please suggest