Hi Team,
I have started looking into parametrized /configurable designs verification in UVM and came across some papers using Abstract-Concrete approach .
But i am missing the lack of understanding of parameterization classes in UVM . we can simply create a parameterized {Agent :: driver, seqr, mon} and we can use a shared parameter file (RTL-DUT) to import the parameters. Why this approach is not recommended ? Please provide with simple example
2. If we want to pass the parametrized interface through uvm_config_db the above parameterized class concept works right . why are we going for Abstract-Concrete approach.
I have read the paper on the Abstract -concrete approach but couldn’t understand why parameterized class concept is recommended and how this Abstract-concrete approach will resolve this ?
Please help with simple practical example
Thanks in Advance