in sv we use new to create object so what is the use of build phase in uvm it provide any extra benefit?
The UVM build phase provides more advantages over new by enabling factory based object creation, centralized configuration, hierarchical construction, and phase synchronization. These features make testbenches more flexible, reusable, and scalable, which is critical for verifying complex designs in UVM based environments.
In SystemVerilog, you can only append to the constructor new() when extending a class. However, using the build_phase() method of a component instead of placing everything within the new() constructor enables you to prepend, append, or completely override the method with modified behavior when extending the class.
Thank you @dave_59 @Surya_prakash.Kapireddy