Using of subenv

UVM
1

Is there an example of using sub-env in UVMF project? I write UVMF testbench for 3 module and now I want to verify all modules in a top module using their environment.

2

Take a look at $UVMF_HOME/templates/python/examples

Here you find the YAML to build 3 block level testbenches (block_a, block_b, and block_c) [look in the yaml_files folder]

Then there is YAML to build the chip level testbench, which uses the block_a and block_b environments as sub-environments.

Look in the chip_env_cfg.yaml

  ## Declare subenvironments. Parameterized sub-environments (such as block_b shown here)
  ## may require that their parameters be defined here.
  subenvs :
    - name: "block_a_env"
      type: "block_a"
    - name: "block_b_env"
      type: "block_b"
      parameters:
        - name: "CP_IN_DATA_WIDTH" 
          value: "CHIP_CP_IN_DATA_WIDTH" 
        - name: "CP_IN_ADDR_WIDTH" 
          value: "CHIP_CP_IN_ADDR_WIDTH" 
        - name: "CP_OUT_ADDR_WIDTH"
          value: "CHIP_CP_OUT_ADDR_WIDTH"
        - name: "UDP_DATA_WIDTH"   
          value: "CHIP_UDP_DATA_WIDTH"

You will be able to build and compile/simulate the chip level TB and see how it works.

3

Thank you