UVM driver for a simple valid-ready protocol

UVM
1

Hi,
I am a beginner. I am trying to write a custom UVM driver for a simple valid -ready protocol. Could someone let me know if the logic is correct or proof read and correct the implementation for the interface protocol which is specified as-

  • When data is available assert the valid
  • Keep the data stable and valid high until ready is asserted
  • De-assert the valid once ready is asserted
    The interface is given as follows
interface intf
input clk;
logic [15:0] Data;
logic        Valid;  
logic        Ready; //coming from the DUT
endinterface

class req_txn extends uvm_sequence_item;
  
  rand logic [15:0] data;
  `uvm_object_utils_begin(req_txn)
  	`uvm_field_int(data, UVM_ALL_ON);
  `uvm_object_utils_end
  
  function new(string name="txn");
    super.new(name);
  endfunction
  
  virtual function void do_print(uvm_printer printer);
    super.do_print(printer);
    printer.print_field_int("data", data, $bits(data), UVM_HEX);
  endfunction
endclass

class my_driver extends uvm_driver #(req_txn);
  `uvm_component_utils(my_driver)
  virtual interface intf vif;
  req_txn               txn_to_send;
  function new(string name="my_driver", uvm_component parent);
    super.new(name, parent);
  endfunction 
  
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    if (!(uvm_config_db#(virtual interface intf)::get(this,"","vif", vif)))
      `uvm_fatal("my_driver", "Unable to get the vif from config db")
  endfunction
   
   virtual task run_phase(uvm_phase phase);
      super.run_phase(phase);
      forever begin
        phase.raise_objection(this);
        seq_item_port.get_next_item(txn_to_send);
        txn_to_send.print();
        @(posedge vif.clk);
        vif.valid <= 1 ;
        vif.data  <= txn_to_send.data;
        wait(vif.ready == 1);
        @(posedge vif.clk);
        vif.valid <= 0;
        seq_item_port.item_done();
        phase.drop_objection(this);
      end
   endtask
endclass

Thank you for your time.