Latest UVM topics - Verification Academy

Topic	Replies	Views	Activity
A better way of getting response back to a waiting sequence?	2	66	April 18, 2024
** Error: /vobs/ss_restart_vseq.sv(714): 'pass_ssr_vseq' is not a task name UVM	3	43	April 18, 2024
How to manage compare policies if uvm_comparer should be avoided? compare , uvm_comparer , do_compare	0	41	April 17, 2024
Driver sequencer communication in uvm	4	75	April 16, 2024
[UVM/REG/DUPLROOT] There are 2 root register models named "reg_model". The names of the root register models have to be unique SystemVerilog , UVM , uvm_reg , RAL-UVM	1	987	April 16, 2024
Override by sequence type changes handle type everywhere whereever it is declared in driver even if it is parameterized or how?	2	43	April 16, 2024
Backdoor access to a reg inside an unnamed primitive	4	97	April 15, 2024
Scoreboard sampling	2	79	April 14, 2024
How to use a variable in uvm test and same variable in the sequence	2	73	April 12, 2024
Function New Constructor SystemVerilog , UVM	1	67	April 11, 2024
Null object reference - Mod 12 Counter design Verification	2	55	April 11, 2024
Configuring Sequences \| UVM Cookbook - question on example code uvm_config_db	1	58	April 10, 2024
Interview Question on UVM	4	110	April 8, 2024
UVM RAL Register Name Access UVM	4	62	April 8, 2024
DUT reference model location? SystemVerilog , UVM	2	74	April 7, 2024
UVM Agent without a sequencer	1	66	April 7, 2024
UVM RAL \| Errors in REG & RAL FILES UVM	1	67	April 6, 2024
Best Practice for Unit Tests Extending Chip-Level Tests SystemVerilog , Inheritance	1	67	April 6, 2024
Memory usage keeps increasing as test runs UVM	5	83	April 4, 2024
UVM severity override from UVM_INFO to UVM_ERROR and UVM_VERBOSITY == UVM_NONE	2	62	April 4, 2024
Read data driving issue in reactive slave of AHB	2	68	April 4, 2024
Uvm_mem reference codes RAL-UVM	2	104	April 4, 2024
UVM run_test Method SystemVerilog	2	63	April 3, 2024
Reuse non-UVM classes in UVM environment UVM	4	74	April 3, 2024
Scoreboard for 2x2 router	5	110	April 2, 2024
How to build a reference model for uvm_scoreboard which perform multi-stage calculation SystemVerilog	0	70	March 30, 2024
Is it valid to pass uvm_component parameter while creating instance of a sequence? uvm_sequence , seq	6	82	March 30, 2024
Is it better to have 1 generic transaction or several specific ones?	0	57	March 29, 2024
Using non-UVM agents in a UVM environmet UVM , hierarchy , configdb , agent	1	1213	March 28, 2024
"Undefined module: <interface> was used. Port connection rules will not be checked at such instantiations." SystemVerilog , UVM , configuration , virtual-interface , interface	2	51	March 27, 2024