Hi, I want to set uvm_mem matched memory in the DUT.
So I want to write/read backdoor data into mem in the DUT.
But, I can’t find uvm_mem example not using uvm_reg
Is it impossible to set uvm_mem not using uvm_reg?
Hi, I want to set uvm_mem matched memory in the DUT.
So I want to write/read backdoor data into mem in the DUT.
But, I can’t find uvm_mem example not using uvm_reg
Is it impossible to set uvm_mem not using uvm_reg?
When you say you want to “set” uvm_mem
, do you mean you want to call the set()
method? There is no such method in uvm_mem
.
Hi, dave
“set” meant setting the uvm environment.
I wanted to control memory in DUT using uvm_mem as a backdoor
It’s a different way, i solved this problem using uvm_hdl_read. but it can’t write. But i don’t need it now
Thank you
Take a look at this EDA example UVM register user-defined memory backdoor; it provides a complete setup for backdoor access.
uvm_mem
backdoor access is in this file my_mem_backdoor.sv
. In your case, if you don’t need to model any registers; then you can directly instantiate the uvm_mem in your environment and configure it, so the environment build_phase
will be something like
function void build_phase(uvm_phase phase);
......
uvm_mem mem;
my_mem_backdoor backdoor;
mem = new("mem", ....);
mem.add_hdl_path_slice("mem", ...);
// other uvm_mem configuration if needed
// Create backdoor and set it
backdoor = my_mem_backdoor::type_id::create("backdoor");
mem.set_backdoor(backdoor);
end
endfunction : build_phase
Thank you Ahmed.
Your answer is very helpful to me.
It’s not a normal way, I can write data using uvm_hdl_deposit as a backdoor without using uvm_mem.