Accessing Derived class members with base class handle

UVM
,
1

Hi,
Can base and derived class have same variable? and Is it possible to access derived class members with base class handle? Do we have any restriction in LRM for these?

// Code your testbench here
// or browse Examples

module top;

  import uvm_pkg::*;
  `include "uvm_macros.svh"
  
class parent_txn extends uvm_sequence_item;
  rand bit [15:0] my_var; // 16-bit in parent
 
  `uvm_object_utils(parent_txn)
 
  function new(string name = "parent_txn");
    super.new(name);
  endfunction
 
  virtual function void display();
    $display("Parent my_var = %0h", my_var);
  endfunction
endclass
 
class child_txn extends parent_txn;
  rand bit my_var; // 1-bit in child (shadows parent's my_var)
 
  `uvm_object_utils(child_txn)
 
  function new(string name = "child_txn");
    super.new(name);
  endfunction
 
  virtual function void display();
    $display("Child my_var = %0b", my_var);
    $display("Parent my_var from child = %0h", super.my_var);
  endfunction
endclass


class my_sequence extends uvm_sequence;
  parent_txn txn;
 
  `uvm_object_utils(my_sequence)
 
  function new(string name = "my_sequence");
    super.new(name);
  endfunction
 
  task body();
    txn = parent_txn::type_id::create("txn");
 
    // Assign values
    txn.my_var = 1'b1;           
   
 
    // Call display function
    txn.display();
 
    // Add uvm_info to print values
    `uvm_info("SEQ", $sformatf("Child my_var = %0b, Size my_var = %0h", txn.my_var, $bits(txn.my_var)), UVM_LOW)
  endtask
endclass



class my_test extends uvm_test;
  `uvm_component_utils(my_test)
 
  parent_txn txn; // Global handle
 
  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction
 
  virtual task run_phase(uvm_phase phase);
    my_sequence seq = my_sequence::type_id::create("seq");
    phase.raise_objection(this);
 
    // Factory override to create child_txn
    parent_txn::type_id::set_type_override(child_txn::get_type());
 
    seq.start(null);
 
    // Store the object handle from the sequence
    txn = seq.txn;
 
    `uvm_info("SEQ", $sformatf("Child my_var = %0b, Size my_var = %0h", txn.my_var, $bits(txn.my_var)), UVM_LOW)
    
    phase.drop_objection(this);
  endtask
 
endclass


  initial begin
    run_test("my_test");
  end
endmodule
2

Although the LRM allows declaring variables with the same name in both a base class and extended classes, it’s generally a bad practice. Make them random variables, and it becomes a terrible idea.

If you have constraints in the base class, they only apply to the base class variable. If you add a declaration in the extended class that does not override anything in the base class–you have two independent variables.

The only way to access extended class members from a base class variable is using a virtual method.

3

why members of extended class can be accessed by virtual method and not by handle directly? Is it a SV limitation?