Using `uvm_error before start_of_simulation

UVM
1

Hi Forum,
We are using verissimo tool which helps catch coding & linting issues.
Eg: If user uses ‘===’ during comparison of 2-state type the tool would throw an error.

One such error I observe if when user were to use `uvm_error in constructor or during build / connect / end_of_elaboration phase.
The tool suggests to use `uvm_fatal instead of `uvm_error.
I do understand that if fetching of tb_config / virtual interface is unsuccessful, ideally one should use `uvm_fatal ( else one might run into Null Object access run-time error )
But are there cases where one could get away with using `uvm_error instead of `uvm_fatal ?

2

If you have an “error” in the testbench components construction and connections it should be classified as fatal error (high severity), I agree.

Examples when you could get away with using uvm_error instead of uvm_fatal:

  1. A packet output from DUT has different values than expected values.
    This error should be debugged, but test could still continue running, so it is not fatal error.
  2. A counter which count number of inflight transactions, is decreased below zero. Once again it is error but not a fatal one.
3

I believe these are cases related to time consuming phases ( run_phase or it’s sub-phases )
My question was related to using `uvm_error in constructor or during build / connect / end_of_elaboration phase.

4

You can use uvm_error and uvm_fatal in any phase, as far as I know, whether a phase is time-consuming or not to its error severity.
No connection between these 2 subjects.

5

Typically, a fatal message means there’s a problem with the test bench–any results you get after the message would be undefined and proceeding does not make any sense.

An error message usually means that the design does not meet the specified requirements. Simulating further may help with analysis of the problem. Also, some people want to catch as many errors as possible in one simulation without having to restart.