Latest UVM topics - Verification Academy

Topic	Replies	Views	Activity
UVM 1800.2 (2020.3.1) - Individual accesses have wrong addresses SystemVerilog , UVM , uvm-register-model	2	102	November 13, 2025
Individual field access causes extra reads/writes? SystemVerilog , UVM , uvm-register-model	5	62	November 12, 2025
UVM RAL: How to execute register access without updating mirrored value? UVM-RAL-UVM	1	112	November 8, 2025
Code debug help	2	110	November 5, 2025
Vertical re-use (from block to sub-system/chip level) UVM , reuse	5	3414	November 2, 2025
Migrating from IP to sub-system level	2	116	November 2, 2025
Why uvm_object_registry is called as lightweight proxy? UVM	1	86	October 28, 2025
UVM Class Hierarchy ? can any one help me by giving me the full uvm base class hierarchy structure UVM	5	178	October 27, 2025
Question on use of RAL model for System-On-Chip verification	4	195	October 24, 2025
Multiple analysis ports to single implementation SystemVerilog , UVM , analysis-port	8	317	October 23, 2025
How to properly extend a test case from different parents SystemVerilog , UVM	2	179	October 21, 2025
How to deep copy UVM transaction containing queue of objects? SystemVerilog , UVM	3	136	October 21, 2025
How to use multiple sequences to override base test	14	271	October 17, 2025
Config db fatal isssue OVM , SystemVerilog , UVM	1	117	October 16, 2025
Clarification on sequence execution flow UVM cookbook figure	6	114	October 16, 2025
Getting last transaction in consumer repetitively even though producer is sending all transaction SystemVerilog , UVM	3	111	October 15, 2025
Getting the virtual interface in the test class or in the agent?	1	88	October 9, 2025
Protected registers behavior implementation with RAL UVM	1	81	October 8, 2025
Query on Register wr/rd verification by taking security state into consideration RAL	2	84	October 8, 2025
Write method as task	6	132	October 8, 2025
Updating UVM Component properties via Field Automation Macros apply_config_settings , field-macros , UVM-field-macros , superbuild_phase	7	105	October 8, 2025
Delay in update of mirrored value in explicit prediction RAL , prediction-monitor-scoreboard , RAL-UVM-PREDICTOR	7	100	October 8, 2025
Backdoor Read consumes simulation time RAL , UVM_BACKDOOR , uvm_ral	2	148	October 8, 2025
Cannot pass struct through uvm_config_db uvm-config_db	3	96	October 3, 2025
How to associate callbacks with analysis ports in a layered UVM protocol for error injection	0	52	October 2, 2025
How to find the functional coverage of a signal which is declared in a module. This module is instantiated 256 times UVM	6	104	October 2, 2025
Can UPF functions be used in uvm sequence class	1	76	September 30, 2025
Accessing variables in overridden class	1	68	September 29, 2025
Facing error when passing arguments in the hierarchy when using $assertoff UVM , assetions , assertoff	2	370	September 27, 2025
Project for self practice for creating TB UVM	1	103	September 25, 2025