VCS Mixed Simulation VCS VHDL Verilog Mixed language simulation with UVM

UVM
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This is to state that I am currently working on Mixed-Design (Containing VHDL && Verilog Files) Verification using SVerilog/UVM Testbench.

After building the initial verification environment when I compile the design & TB files together through Makefile script it gives an error that TB top is not able to find the Design instantiation? My design includes a VHDL top with a Verilog file instantiated in it.

I make separate flist files for Verilog VHDL & SVerilog files.

How do I link compiled design (VHDL & Verilog) && UVM testbench files?

My Makefile commands are mentioned below:

vlogan -work work +v2k +incdir+(UVM_HOME) (UVM_HOME)/uvm_pkg.sv +libext+.sv -f ./results/vlog_flist.f -ntb_opts uvm-1.2 -full64 -debug_all

vhdlan -work work -f ./results/vhdl_flist.f

vcs -timescale=1ns/1ps -f ./results/build_uvc.f -error=noZONMCM -ntb_opts uvm-1.2 -sverilog -cm line+cond+tgl+fsm -ova_cov -cm_hier config_covg.cfg -cm_name ${TEST} -LDFLAGS -Wl,–no-as-needed -debug_all

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