Seq.start(seqr) is not starting the seq body

UVM
1

Hi, I have an env where we have. two identical drivers and their identical sequencers

m_master_tlm_drv[i]= master_tlm_driver::type_id::create($psprintf(“m_master_tlm_drv_%0d”,i),this);
m_sqr[i] = uvm_sequencer#(my_item)::type_id::create($psprintf(“m_sqr_%0d”,i),this);

I have a seq which I want to start in parallel on both these sequencers

code in test.sv

    my_item_seq seq1 = my_item_seq::type_id::create("seq1");
    my_item_seq seq2 = my_item_seq::type_id::create("seq2");
    phase.raise_objection(this);
    
    `uvm_info(get_type_name(),$sformatf(" BEFORE STARTING SEQUENCE"),UVM_LOW)

    assert(seq1.randomize());
    assert(seq2.randomize());
    `uvm_info(get_type_name(),$sformatf(" SEQ1 NUM = %0d, SEQ2_NUM=%0d",seq1.num,seq2.num),UVM_LOW)
    fork
      seq1.start(m_env.m_sqr[0]);  // seqr is  instantoated directly in ENV
      seq2.start(m_env.m_sqr[1]);
    join_none
    `uvm_info(get_type_name(),$sformatf(" SEQUENCES KICKED OFF"),UVM_LOW)
    wait fork;
      `uvm_info(get_type_name(),$sformatf(" DROPPING OBJECTION"),UVM_LOW)
    phase.drop_objection(this);

SEQ ITEM is as follows

class my_item extends uvm_sequence_item;
  rand int   	    A;
 rand int   	    B;
 rand int   	    C;
 // Use utility macros to implement standard functions
 // like print, copy, clone, etc
  `uvm_object_utils_begin(my_item)
  `uvm_field_int (A, UVM_DEFAULT)
  `uvm_field_int (B, UVM_DEFAULT)
  `uvm_field_int (C, UVM_DEFAULT)
  `uvm_object_utils_end
  
  function new(string name = "my_item");
    super.new(name);
  endfunction
endclass

BASE SEQ is

class my_item_seq extends uvm_sequence#(my_item);
  `uvm_object_utils(my_item_seq)
  function new(string name="my_item_seq");
    super.new(name);
  endfunction
  
  rand int num; 	// Config total number of items to be sent
  
  constraint c1 { num inside {[200:500]}; }
  
  virtual task body();
    super.body();
    `uvm_info(get_type_name(), $sformatf("ENTERED SEQ BODY"), UVM_LOW)
    for (int i = 0; i < num; i ++) begin
      my_item m_item = my_item::type_id::create("m_item");
    	start_item(m_item);
      assert(m_item.randomize());
      `uvm_info("BASE_SEQ", $sformatf("Generate new item: "), UVM_LOW)
    	m_item.print();
      	finish_item(m_item);
    end
    `uvm_info("BASE_SEQ", $sformatf("Done generation of %0d items", num), UVM_LOW)
  endtask
endclass

I am using EDA playground cadence simulator. when I start the test , I get

UVM_INFO base_test.sv(31) @ 0: uvm_test_top [base_test]  BEFORE STARTING SEQUENCE
UVM_INFO base_test.sv(35) @ 0: uvm_test_top [base_test]  SEQ1 NUM = 302, SEQ2_NUM=357
UVM_INFO base_test.sv(40) @ 0: uvm_test_top [base_test]  SEQUENCES KICKED OFF
Execution interrupted or reached maximum runtime.
Exit code expected: 0, received: 137

Not sure what am I missing here

2

Hi,

What is the timescale you used?

-Rajratna

3

I used
-timescale 1ns/1ns -sysv

5

Can you share the driver code or better still the edaplayground link ?

7

Driver code

class mydriver extends uvm_driver#(packet_item);
  
  virtual my_intf#(num) vif;
  `uvm_component_utils(my_driver)
  uvm_analysis_port #(my_item) drv2scb;

  function new( string name, uvm_component parent);
    super.new(name,parent);
  endfunction
  
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    if (!uvm_config_db#(virtual my_intf#(num))::get(this, "", "vif", vif))
      `uvm_fatal("get_type_name()", "Could not get vif")
      drv2scb = new("drv2scb",this);
  endfunction
 
  
  virtual task run_phase(uvm_phase phase);
    super.run_phase(phase);
    forever begin
      my_item m_item; 
      seq_item_port.get_next_item(m_item);
      //Task to drive the interface
      drv2scb.write(m_item); // send to scoreboard
      seq_item_port.item_done(m_item);      
    end    
  endtask
endclass
9

You have a zero-delay loop somewhere in your testbench, as seen by the message that you have reached maximum runtime. When this occurs, you won’t see all the messages printed since EDA playground will kill your run without flushing the output buffer.

You will need to provide the EDA playground link so that the entire environment can be reviewed.

1 Like
10

here is the link

11

Your environment is private. You will need to make it public so that others can view it.

12

please try now

13

Your issue is in packet_mux_scoreboard. The section marked SCOREBOARD MAIN CHECK has a zero delay loop which never blocks to allow time to advance.

Several additional comments:

  • Never use an interface in your scoreboard. It should only be transactional based.
  • You don’t need to create any watchdog. UVM has built-in timeout capabilities that you can adjust as needed.
2 Likes
14

Thanks @cgales .
It works now. Thanks for the additional comments