Race condition when two threads access an uvm reg

UVM
1

I have 2 threads :
In one thread,
I do a continuous read on a register :
do
regA.read(status,rd_data);
while (rd_data!=0)

In another thread,
I do a write :
begin
regA.write(status,1);
end

It so happens that these 2 threads execute simultaneously and I get the below warning :
W:: UVM/FLD/SET/BSY: Setting the value of field “XXX” while containing register “YYY” is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
And, the wdata of 1’b1 does not propagate to the regA.

2

You can try using semaphores so that the field wont be accessed at the same time

3

Thanks . Sure that will work . But I was wondering why UVM RAL cannot handle it internally ?

4

You can use the regA.is_busy() fucntion to check if the register is currently being accessed and based on the value you either wait or proceed with the reg access.