Clocking Block in UVM Driver

UVM
1

Hi,
would there be any difference in the way it runs in the following two codes.
In code-1 , forver @(vif.cb) is used with while() loop
In code-2 , forver is used with do-while() loop
Which way is better with clocking blocks ?
Code-1

task run_phase(uvm_phase phase)
   forever @(vif.cb) begin
            seq_item_port.try_next_item(item);
           if(item != null) begin
               vif.cb.valid <=1;
               vif.cb.data <=item.data;

               while(vif.cb.enable == 1'b0) @(vif.cb);

               seq_item_port.item_done()          


           end
           else begin
                vif.cb.valid <=0;
               @(vif.cb);
           end
   end
endtask

code-2

task run_phase(uvm_phase phase)
   forever begin
            seq_item_port.try_next_item(item);
           if(item != null) begin
               vif.cb.valid <=1;
               vif.cb.data <=item.data;

               do
                  @(vif.cb);
               while(vif.cb.enable == 1'b0) ;

               seq_item_port.item_done()          


           end
           else begin
                vif.cb.valid <=0;
               @(vif.cb);
           end
   end
endtask
2

I don’t see a clear preference of one over the other, however, there is a subtle/key diff in functionality - if the enable was high, code-2 would wait for a clock, code-1 won’t.