Interface is not updating the value

SystemVerilog
1

In my base test code i am accessing the top interface and updating the value of vsp variable of the interface but it is only taking limit value not updating the correct limit - (1/6) value as needed.

What can be the issue?

top_vif.vsp =  limit - (1/6);

Thanks.

2

What are the data types of the variables? Can you give us an example of the values you’re expecting?

3

Hi dave,

vsp is real variable and limit is int variable.

4

It’s a truncation issue. Just replace it with

top_vif.vsp =  type(top_vif.vsp)'(limit - (1.0/6.0));

Be ware that this will round the value, meaning that .8 will be rounded to 1. You can use $floor() if you don’t want this behavior (and I am guessing that you don’t):

top_vif.vsp = type(top_vif.vsp)'($floor(limit - (1.0/6.0)));

If you also need it to be synthesizable (being an interface) you can do something like:

real tmp = (limit - (1.0/6.0); top_vif.vsp = type(top_vif.vsp)'(tmp > limit - 0.5 ? tmp - 1.0 : tmp);
5

Be ware that this will round the value, meaning that .8 will be rounded to 1. You can use $floor() if you don’t want this behavior (and I am guessing that you don’t):

top_vif.vsp = type(top_vif.vsp)'($floor(limit - (1.0/6.0)));

If you also need it to be synthesizable (being an interface) you can do something like:

real tmp = (limit - (1.0/6.0); top_vif.vsp = type(top_vif.vsp)'(tmp > limit - 0.5 ? tmp - 1 : tmp);
6

Because limit is an integer you have to cast this to real, like this: