D flip flop with active low reset and enable signal to capture the data

SystemVerilog
1 
module register (input logic [7:0] data,
                 input logic rst ,
                 input logic clk, 
                 input logic enable,
                 output logic [7:0] out); 
  
    timeunit 1ns;
    timeprecision 1ps;
  
  always @(posedge(clk) )
    begin: register_logic
      if (~rst)
        out <= 8'b0;
      else if (enable == 1)
        out <= data;
      
    end : register_logic 
  
endmodule : register

TB :

module tb ();
  timeunit 1ns/1ps;
  timeprecision 1ps;
  parameter CLK_PERIOD = 10;
  reg [7:0] data;
  reg clk , rst , enable;
  wire [7:0] out ;
  
  
  
  initial
    begin: initialise
      data <= 8'bx;
      rst <= 1'b1;
      enable <= 1'bx;
      clk <= 1'b0;
    end: initialise
  
	always
    begin 
      #(CLK_PERIOD/2) clk = ~clk;
    end
  
 
  
  register dut (.*
  				);
      	//$printtimescale(dut);			  
  initial 
    begin: monitor
     $timeformat(-12,5,"ps",2);
      $monitor ("time = %t enable = %b rst = %b data = %h out = %h ", $time,enable, rst, data, out);
    end: monitor
   
 /* initial 
    begin : dump
      $dumpfile("dump.vcd");
      $dumpvars(0,tb);
    end : dump
  */
  
  initial
    begin: vector
      #15 rst <= 1'b0;
      #10 rst <= 1'b1 ; enable <= 1'b0;
      #10 data <= 8'haa; enable <= 1'b1;
      /*#10 data <= 8'h55; enable <= 1'b0;
      #10 rst <= 1'b0; data <= 8'hx; enable <= 1'bx;
      #10 rst <= 1'b1; data <= 8'hx; enable <= 1'b0;
      #10 data <= 8'h55; enable <= 1'b1;
      #10 data <= 8'haa; enable <= 1'b0;
      #1.23456 data <= 8'h8;*/ 
      #20 $finish;
      
    end: vector
  
endmodule : tb

log :

time = 0.00000ps enable = x rst = 1 data = xx out = xx 
time = 15000.00000ps enable = x rst = 0 data = xx out = xx 
time = 25000.00000ps enable = 0 rst = 1 data = xx out = 00 
time = 35000.00000ps enable = 1 rst = 1 data = aa out = 00 
time = 45000.00000ps enable = 1 rst = 1 data = aa out = aa

tb :

// Code your testbench here
// or browse Examples
module tb ();
  timeunit 1ns/1ps;
  timeprecision 1ps;
  parameter CLK_PERIOD = 10;
  reg [7:0] data;
  reg clk , rst , enable;
  wire [7:0] out ;
  
  
  
  initial
    begin: initialise
      data <= 8'bx;
      rst <= 1'b1;
      enable <= 1'bx;
      clk <= 1'b0;
    end: initialise
  
	always
    begin 
      #(CLK_PERIOD/2) clk = ~clk;
    end
  
 
  
  register dut (.*
  				);
      	//$printtimescale(dut);			  
  initial 
    begin: monitor
     $timeformat(-12,5,"ps",2);
      $monitor ("time = %t enable = %b rst = %b data = %h out = %h ", $time,enable, rst, data, out);
    end: monitor
   
 /* initial 
    begin : dump
      $dumpfile("dump.vcd");
      $dumpvars(0,tb);
    end : dump
  */
  
  initial
    begin: vector
      #15 rst = 1'b0;
      #10 rst = 1'b1 ; enable = 1'b0;
      #10 data = 8'haa; enable = 1'b1;
      /*#10 data <= 8'h55; enable <= 1'b0;
      #10 rst <= 1'b0; data <= 8'hx; enable <= 1'bx;
      #10 rst <= 1'b1; data <= 8'hx; enable <= 1'b0;
      #10 data <= 8'h55; enable <= 1'b1;
      #10 data <= 8'haa; enable <= 1'b0;
      #1.23456 data <= 8'h8;*/ 
      #20 $finish;
      
    end: vector
  
endmodule : tb

log

time = 0.00000ps enable = x rst = 1 data = xx out = xx 
time = 15000.00000ps enable = x rst = 0 data = xx out = 00 
time = 25000.00000ps enable = 0 rst = 1 data = xx out = 00 
time = 35000.00000ps enable = 1 rst = 1 data = aa out = aa

My question here is why when using blocking statement to pass the value to dut will spoil the synchronous nature of flip flop

I have already read a post regarding it can cause race condition for flip flop because of this output is effect but it should not act like this

2

Instead of using $monitor(...), use forever @(posedge clk) $display(...)

3

Hi @dave_59 you suggested the above because monitor comes in the monitor queue and that comes last in order of event queue or any other reason ?

4

Yes, $monitor prints values at the end of the time slot, it won’t show differences between blocking an d nonblocking assignments.

5

[quote=“dave_59, post:4, topic:50296”]
s, $monitor prints values at
[/quote]Thanks for the reply but I feel some times the language create ambiquity if you have designed it correct or not, for example here just simple d flip with linear testbench create ambiquity of the design is a flip flop or latch but in complex design where the exact determination of functionality is not simple then what approach should we keep to avoid these type of ambiquities