Initializing a multi-dimentional array to all zeros

SystemVerilog
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1 
 logic signed [WIDTH : 0] rg      [I] [J] ;

WIDTH, I, J are parameters. How can I initialise the above array to all zeroes. I know I can do it using nested for loops. But I would like to know the shortest version in System Verilog to achieve it.

2

In reply to Mitu Raj:

logic signed [WIDTH : 0] rg      [I] [J] = '{default:0};