logic signed [WIDTH : 0] rg [I] [J] ;
WIDTH, I, J are parameters. How can I initialise the above array to all zeroes. I know I can do it using nested for loops. But I would like to know the shortest version in System Verilog to achieve it.
logic signed [WIDTH : 0] rg [I] [J] ;
WIDTH, I, J are parameters. How can I initialise the above array to all zeroes. I know I can do it using nested for loops. But I would like to know the shortest version in System Verilog to achieve it.
In reply to Mitu Raj:
logic signed [WIDTH : 0] rg [I] [J] = '{default:0};
Hi @dave_59 Is this synthesizable solution?
It depends. An initialization in a variable declaration is supported as a power on reset in some synthesis tools, mainly for FPGAs.