Hi.
I have a parameterized design module that a colleague wrote,
and I have an assertions module (also parameterized) that I want to instance into his code - without modifying it (i.e. using systemverilog bind).
How can I do the bind of the parameters?
Thanks,
In reply to Yoram-Stern:
Hi.
I have a parameterized design module that a colleague wrote,
and I have an assertions module (also parameterized) that I want to instance into his code - without modifying it (i.e. using systemverilog bind).
How can I do the bind of the parameters?
Thanks,
The syntax for the bind is:
syntax for the bind construct is as follows:
bind_directive4 ::=
bind bind_target_scope [: bind_target_instance_list] bind_instantiation ;
| bind bind_target_instance bind_instantiation ;
bind_target_scope ::=
module_identifier
| interface_identifier
bind_target_instance ::=
hierarchical_identifier constant_bit_select
bind_target_instance_list ::=
bind_target_instance { , bind_target_instance }
bind_instantiation ::=
program_instantiation
| module_instantiation
| interface_instantiation
| checker_instantiation
Below is a complete example from my SVA book.
module counter (output logic[2:0] count_out, // counter output
input logic[2:0] data_in, // data to load
input logic ld_enb, count_enb, rst_n, clk);
timeunit 1ns; timeprecision 100ps;
logic [2:0] count;
logic tc;
assign count_out =count;
assign tc = count==3'b111;
default clocking @(negedge clk); endclocking
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) count <= 0;
else if (ld_enb) count <= data_in;
else if (count_enb) count <= count_out + 1;
end
endmodule // counter
module counter_props (
input logic[2:0] count_out, // counter output
input logic ld_enb, rst_n,
input logic [2:0] count, // internal design signal
input logic tc, // internal design signal
input logic clk
);
timeunit 1ns; timeprecision 100ps;
property p_tc;
disable iff (!rst_n)
(count)==3'b111 |-> tc;
endproperty : p_tc
ap_tc : assert property(@ (posedge clk) p_tc) else
$display ("0t error in terminal count", $time);
ap_counter : assert property( @ (posedge clk) tc |-> ##8 tc);
default clocking @(negedge clk); endclocking
endmodule : counter_props
module counter_tb;
timeunit 1ns; timeprecision 1ns;
logic ld_enb=0;
logic [2:0] data_in;
wire [2:0] count_out;
logic count_enb=0;
logic clk=0;
logic rst_n=1;
initial forever #10 clk=!clk;
counter
DUT (
.ld_enb (ld_enb ) ,
.data_in (data_in ) ,
.count_out (count_out ) ,
.count_enb (count_enb ) ,
.clk (clk ) ,
.rst_n (rst_n ) );
bind counter counter_props counter_props_1(
.count_out(count),
.ld_enb(ld_enb),
.rst_n(rst_n),
.count(count),
.clk(clk),
.tc(tc));
default clocking @(negedge clk); endclocking
initial begin
##1;
data_in <= 8'hF0;
ld_enb <= 1;
count_enb <= 1'b1;
##1;
ld_enb <= 1'b0;
end
endmodule : counter_tb
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
In reply to Yoram-Stern:
A bind module instance statement works just as if you had module instance statement inside the target module. So you can reference the targets parameters and pass them to the bind instance.
module DUT #(int tP)();
endmodule
module to_bind #(int bP)();
initial $display("%m %d",bP);
endmodule
module top;
DUT #(1) d1();
DUT #(2) d2();
DUT #(3) d3();
bind DUT to_bind #( .bP(tP) ) instname();
endmodule
In reply to dave_59:
Hi All,
Can we bind three components simultaneously? Like,
bind DUT_Isnt Assertion_module intf_h bind_sign(.*)
if not then is there any suitable way to access interface handle in assertion module file?
In reply to mitesh.patel:
I do not understand your question. What are the three components? What do you mean by “interface handle” Perhaps you should start a new topic and show a more complete example.
In reply to mitesh.patel:
As far as I get your question, here is my guess in its explanation. Binding is like instantiating some entity inside some other module without changing the physical code of the parent module.
If you don’t specify module instance in bind statement, then the bind will apply to all the instances of parent module.
bind DUT Assertion_module myassertion(.*) // This will bind to ALL the instances of the module "DUT"
bind DUT:inst Assertion_module myassertion(.*) // This will bind to only "inst" instance of the module "DUT"
Refer to this pdf for more information.
In reply to sharvil111:
Thanks sharvil111 for help.
I also encountered a similar issue and solved the compilation error by following your example. Thank you very much!