How to bind parameterized module

SystemVerilog
3

In reply to Yoram-Stern:

A bind module instance statement works just as if you had module instance statement inside the target module. So you can reference the targets parameters and pass them to the bind instance.

module DUT #(int tP)();
endmodule
module to_bind #(int bP)();
   initial $display("%m %d",bP);
endmodule
module top;
   DUT #(1) d1();
   DUT #(2) d2();
   DUT #(3) d3();

   bind DUT to_bind #( .bP(tP) ) instname();

endmodule
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