Constraining address generation for each block of memory in cyclic order

SystemVerilog
, ,
1

I want to generate 4 different addresses for a 512 block of memory which is divided into 4 groups each of 128 locations. Each address has to be incremental in the sense if each block is indexed addresses has to be generated for incremental indices in cyclic order.

I am using following code but unable to provide incremental index.

module top;

class addr_constraint;

rand bit [8:0] addr;
rand int unsigned i;

constraint addr_c {
addr inside {[127*(i+1) : 127*i]}; i<4; solve i before addr;}

endclass

addr_constraint addr_con = new;
initial repeat(4) begin
if(!addr_con.randomize) $error(“Address Randmization failed \n”);
$display(“addr is %0x for itr %0d”,addr_con.addr,addr_con.i);
end

endmodule : top

However i am getting following error:

Error: “testbench.sv”, 18: top: at time 0 ns
Address Randmization failed

addr is 0 for itr 0

2

There is no error when I change the order inside the square brackets (“i” to the left, “i+1” to the right):

    addr inside {[127*i : 127*(i+1)]};
3

@gsulliva Thank you for sharing. Now i got expected output through this code:

module top;

class addr_constraint;
  
  rand bit [8:0] addr;
  randc bit unsigned [1:0] i;
  
  constraint addr_c {
    addr inside {[127*i : 127*(i+1)]};}
  
endclass

  addr_constraint addr_con = new;
  initial repeat(4) begin
  	if(!addr_con.randomize) $error("Address Randmization failed \n");
    $display("addr is %0d for itr %0d",addr_con.addr,addr_con.i);
  end
  
endmodule : top

output :

addr is 456 for itr 3
addr is 230 for itr 1
addr is 272 for itr 2
addr is 93 for itr 0