Percentage weighted distribution of SV Constraints

SystemVerilog
, , ,
1 
class disttest;
	rand bit [2:0] addr;

	constraint c1 { addr dist {[0:5] := 6, [6:7] := 4}; }
	covergroup cg (); //@(posedge clk);
		coverpoint addr;
	endgroup

endclass

module top();
  bit clk;
  int addrq[$], addr1q[$], res1[$], res2[$];
  always #10 clk = ~clk;

initial begin
	disttest tc;
	tc = new();
	for(int ii=0; ii<10; ii++) begin
		tc.randomize();
		addrq.push_back(tc.addr);
	end
		res1 = addrq.find(x) with (x>5);
		res2 = addrq.find(x) with (x<6);
		$display("%p, %p",res1, res2);
		
end

endmodule

Results:
//20 iterations of for loop produced: '{6, 7, 6, 6, 6}, '{4, 1, 2, 5, 2, 1, 0, 2, 3, 2, 3, 4, 0, 2, 5}
//10 iterations produced: '{6, 7, 6, 6, 6}, '{4, 1, 2, 5, 2}

I expected it to generate 6,7 values - 4 times and any value between 0-5 - 6 times.
Is the test expect wrong?

2

In reply to natasv:

class disttest;
    rand bit [2:0] addr;
    constraint c1 { addr dist {[0:5] :/ 6, [6:7] :/ 4}; }
    covergroup cg (); //@(posedge clk);
        coverpoint addr;
    endgroup
endclass

module top();
  bit clk;
  int addrq[$], addr1q[$], res1[$], res2[$];
  always #10 clk = ~clk;

  initial begin
	disttest tc;
	tc = new();
        for(int ii=0; ii<1000; ii++) begin
		tc.randomize();
		addrq.push_back(tc.addr);
	end
	res1 = addrq.find(x) with (x>5);
	res2 = addrq.find(x) with (x<6);
        $display("%p, %p",res1.size(), res2.size());	
end

endmodule
3

In reply to yourcheers:

this is not working

4

In reply to natasv:

This is very much probabilistic, when you run for more iterations the probability ratio is more accurate.
When I run this code in eda playground, I see [0:5] is about 599 times, & [6:7] is about 401 times, that is 6:4 ratio. what is not working for you in this?

5

In reply to natasv:

See Constraint for a random variables | Verification Academy