Percentage weighted distribution of SV Constraints

SystemVerilog
, , ,
2

In reply to natasv:

class disttest;
    rand bit [2:0] addr;
    constraint c1 { addr dist {[0:5] :/ 6, [6:7] :/ 4}; }
    covergroup cg (); //@(posedge clk);
        coverpoint addr;
    endgroup
endclass

module top();
  bit clk;
  int addrq[$], addr1q[$], res1[$], res2[$];
  always #10 clk = ~clk;

  initial begin
	disttest tc;
	tc = new();
        for(int ii=0; ii<1000; ii++) begin
		tc.randomize();
		addrq.push_back(tc.addr);
	end
	res1 = addrq.find(x) with (x>5);
	res2 = addrq.find(x) with (x<6);
        $display("%p, %p",res1.size(), res2.size());	
end

endmodule