Topic	Replies	Views	Activity
Why final phase have top - down execution flow why not bottom-up? UVM UVM_PHASE	1	72	June 13, 2025
Calling of build phase? UVM UVM , UVM_PHASE , build_phase	26	20708	November 14, 2024
Suggestions for uvm_phase API UVM UVM , UVM_PHASE	1	103	July 25, 2024
Why pre_shutdown phase occurs at 0ns? UVM SystemVerilog , UVM , UVM_PHASE , run_phase , shutdown_phase	1	707	July 6, 2022
How uvm phasing mechanism (behind the curtain) work ? can it be achived by systemverilog features? UVM UVM , UVM_PHASE	1	585	February 5, 2022
Scheduling in build_phase() UVM UVM , uvm-uvm_config_db , UVM_PHASE , event-scheduling	1	692	September 7, 2021
Handle as null UVM UVM , UVM_PHASE , uvm_component , UVM-task-phase-execute , uvm_component-parent--null	4	2471	March 28, 2020
What happens in the build phase? UVM UVM , UVM_PHASE , create	3	2002	November 2, 2016
UVM_Phasing Clarification needed UVM UVM , UVM_PHASE , run_phase	2	1656	November 13, 2015
UVM testcase stops at the extract phase and doesnt exit simulation UVM UVM , UVM_PHASE	2	2907	December 24, 2014
UVM phase UVM UVM , UVM_PHASE	3	2014	September 19, 2014
Phase Doubt: build, connect, start (pre-start, start, post-start), run(......), UVM UVM , UVM_PHASE	2	1922	June 4, 2014
UVM Phases handling question UVM UVM , UVM_PHASE	1	1703	March 31, 2014

UVM_PHASE