Hello ,
We were trying to run simulations on UVM using questasim and we see the packets being sent and received.
The testcase runs fine but for some reasons after dropping all the objections the code just sits at the below line in the uvm_phases.svh
It is stuck at line 1099 in /sw/mentor/questasim/10.3/questasim/Verilog_src/uvm-1-1d/src/base/uvm_phase.svh
which is ‘wait (pred.m_state == UVM_PHASE_DONE);’
The log file message before it halts at the above line are
UVM_INFO @ 7840935 ns: main_objection [OBJTN_TRC] Object uvm_test_top subtracted 1 objection(s) from its total (dropped from source object uvm_test_top.d31_uvm_tb_h.map_gen_env_h.map_gen_scq_agent_h[0].map_gen_sequencer_h.map_gen_main_seq_c, map_gen_main_seq_c): count=0 total=0
UVM_INFO @ 7840935 ns: main_objection [OBJTN_TRC] Object uvm_test_top subtracted 1 objection(s) from its total (all_dropped from source object uvm_test_top.d31_uvm_tb_h.map_gen_env_h.map_gen_scq_agent_h[0].map_gen_sequencer_h.map_gen_main_seq_c, map_gen_main_seq_c): count=0 total=0
UVM_INFO @ 7840935 ns: main_objection [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (dropped from source object uvm_test_top.d31_uvm_tb_h.map_gen_env_h.map_gen_scq_agent_h[0].map_gen_sequencer_h.map_gen_main_seq_c, map_gen_main_seq_c): count=0 total=0
UVM_INFO @ 7840935 ns: main_objection [OBJTN_TRC] Object uvm_top subtracted 1 objection(s) from its total (all_dropped from source object uvm_test_top.d31_uvm_tb_h.map_gen_env_h.map_gen_scq_agent_h[0].map_gen_sequencer_h.map_gen_main_seq_c, map_gen_main_seq_c): count=0 total=0
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1218) @ 7840935 ns: reporter [PH_READY_TO_END_CB] Phase ‘uvm.uvm_sched.main’ (id=256) CALLING READY_TO_END CB
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1356) @ 7840935 ns: reporter [PH_END] Phase ‘uvm.uvm_sched.main’ (id=256) ENDING PHASE
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1381) @ 7840935 ns: reporter [PH/TRC/DONE] Phase ‘uvm.uvm_sched.main’ (id=256) Completed phase
UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_phase.svh(1403) @ 7840935 ns: reporter [PH/TRC/SCHEDULED] Phase ‘uvm.uvm_sched.post_main’ (id=268) Scheduled from phase uvm.uvm_sched.main
Break in Task uvm_pkg/uvm_phase::execute_phase at /sw/mentor/questasim/10.3/questasim/linux_x86_64/…/verilog_src/uvm-1.1d/src/base/uvm_phase.svh line 1099
So please suggest what can be done for this kind of issue, since we tried to put breakpoints in the code and it still reaches this line and sits there…
Looking for a reply since we are stuck with this issue to move ahead.
Regard
Deepak