UVM Phases handling question

UVM
,
1

Hi All,

In addition to the question posed in this link ,Phases in UVM | Verification Academy I would like to know what is the recommended way to handle different sequences to be run during different run-phases of the sequencer?

The sequencer hook for default_sequence is only applicable for the main_phase of the sequencer? If I need to explicitly specify pre_reset_sequence, reset_sequence, post_reset sequence etc all of which need to be run on the same sequencer.
DO I need to take care of this in the test/virtual sequence and explicitly call start() method on each sequence(pre-reset,reset,post_reset etc) on the same sequencer?

Thanks
Venkat

2

Hi Venkat,
We do not recommend setting a default_sequence. However, if you feel you must, you should set the sequence from the test, as follows:


class my_test extends uvm_test;
 `uvm_component_utils(my_test)
...
  virtual function void build_phase(uvm_phase phase);
    my_reset_seq = reset_seq_t::type_id::create("reset_seq");
    // set parameters of my_reset_seq prior to putting it into config_db
    uvm_config_db#(uvm_sequence_base)::set(null, "top.agent.myseqr.reset_phase",
                                           "default_sequence", my_reset_seq);
    ...
  endfunction

You can do something similar for each phase. While it is possible to configure the default_sequence by type:


    uvm_config_db#(uvm_sequence_base)::set(null, "top.agent.myseqr.reset_phase",
                                           "default_sequence", 
                                           reset_seq_t::type_id::get());

but this doesn’t allow you to set up the sequence before it starts.