Phases in UVM

In my driver i have broken run_phase to sub phase like reset_phase and main_phase.
In my test case if i am using run phase it is not driving anything and the test bench is hanged.
But if i am using main_phase instead of run_phase it is working fine.

What can be the possible reason for this problem?

The recommendation is that drivers and monitors should only implement the run_phase. The only thing you should be using main_phase etc. for (and we don’t recommend it) is in the test to control which sequence gets run.
It sounds like you’re in a situation where the test in run_phase is waiting for some handshaking that is prevented by your driver executing something in reset_phase before it gets to main_phase. When you have your test execute main_phase, then whatever it’s doing doesn’t start until after reset_phase has completed.
You driver should just execute run_phase since all it will do is receive transactions from a sequence and put them on the bus. In your test, if you want to do a reset, that should be a specific transaction that the driver recognizes and “does the reset” - whatever that means.

In reply to tfitz:

Hi Tom,

In addition to the question posed above, I would like to know what is the recommended way to handle different sequences to be run during different run phases of the sequencer?

The sequencer hook for default_sequence is only applicable for the main_phase of the sequencer? If I need to explicitly specify preset_sequence, reset_sequence, post_reset sequence etc all of which need to be run on the same sequencer, DO I need to take care of this in the test and explicitly call start() method on each sequence?

Thanks
Venkat

In reply to venkstart:

Actually, the sequencer supports a default_sequence for each phase. But we still don’t recommend you use them. We recommend that you explicitly start each sequence from the appropriate phase in your test.