Suggestions for uvm_phase API

UVM
,
1

Hi,
Within a component I have 2 analysis_imps ( using `uvm_analysis_imp_decl macro )

 int assoc1[int];
 int assoc2[int];

 function void write_desc_req( req_pkt pkt);
    assoc1[pkt.qid] += 1;
   // Some logic
 endfunction

 function void write_sqhd_req( req_pkt pkt);
    assoc2[pkt.qid] += 1;
   // Some logic
 endfunction

Now I am trying to debug the respective phase in which these associative arrays are being populated , so I decided to add a msg within the 2 write functions

function void write_desc_req( req_pkt pkt);
   uvm_phase ph;

    ph = <Some_UVM_API> ; // Need suggestions here
    assoc1[pkt.qid] += 1;
   `uvm_info("MY_DEBUG",$sformatf("assoc1['h%0h] incremented in %0s",pkt.qid,ph.get_name()),UVM_NONE)
   // Some logic
 endfunction

function void write_sqhd_req( req_pkt pkt);
   uvm_phase ph;

    ph = <Some_UVM_API> ; // Need suggestions here
    assoc2[pkt.qid] += 1;
   `uvm_info("MY_DEBUG",$sformatf("assoc2['h%0h] incremented in %0s",pkt.qid,ph.get_name()),UVM_NONE)
   // Some logic
 endfunction

Where ph.get_name() should return string types like ::
pre_reset / reset / post_reset / pre_configure / configure / post_configure /
pre_main / main / post_main / … / pre_shutdown / shutdown / post_shutdown

Does UVM provide any API to fetch the current uvm_phase ?

2

There is no such thing as the current phase since phases can overlap. For debug, you probably want $stacktrace (recently added by the IEEE 1800-2023 SystemVerilog LRM and already supported by many tools.

If that does not give you the information you need, you can create a component whose sole purpose is providing a state representing the phases you want to track.

class phase_tracker extends uvm_component;
...
static string current_phase;
task reset_phase(uvm_phase phase);
   current_phase = phase.get_name;
endtask
task main_phase(uvm_phase phase);
   current_phase = phase.get_name;
endtask
endclass