Topics tagged UPF--power-aware

Topic	Replies	Views	Activity
Best way to waive one signal mismatching isolation value versus reset value SystemVerilog Questa-Power-Aware-Simulator , UPF--power-aware , Low-Power--UPF , UPF , Low-Power-Verification , Questa-Power-Aware	0	57	February 13, 2025
Difference between UPF instrumentation and Instantiation SystemVerilog SystemVerilog , UPF--power-aware , Low-Power--UPF , UPF	1	600	October 21, 2021
I would like to know how many ways we have to debug when anything goes wrong in UPF UVM UVM , UPF--power-aware , Low-Power--UPF	1	609	October 2, 2021
Is there something called power isolation cell and if yes whats the difference between Power isolation cell vs isolation cell UVM UVM , UPF--power-aware , Low-Power--UPF	2	1203	October 17, 2018
We have two domain pd1 at low voltage and pd2 at high voltage, pd1 to pd2 connection has no level shifter, what kind of design bugs and power related bugs can be seen? SystemVerilog SystemVerilog , UPF--power-aware , Low-Power--UPF , UPF , Advanced-Verification	0	1121	November 17, 2017
What type of RTL bugs can be caught using power verification? SystemVerilog SystemVerilog , UPF--power-aware , UPF	2	1920	October 9, 2017
Power Aware: Unable to understand the isolation signal name defined in the UPF file UVM UVM , UPF--power-aware	1	1285	December 22, 2015