Topics tagged UPF--power-aware

Topic	Replies	Views	Activity
Difference between UPF instrumentation and Instantiation SystemVerilog SystemVerilog , UPF--power-aware , Low-Power--UPF , UPF	1	479	October 21, 2021
I would like to know how many ways we have to debug when anything goes wrong in UPF UVM UVM , UPF--power-aware , Low-Power--UPF	1	503	October 2, 2021
Is there something called power isolation cell and if yes whats the difference between Power isolation cell vs isolation cell UVM UVM , UPF--power-aware , Low-Power--UPF	2	1078	October 17, 2018
We have two domain pd1 at low voltage and pd2 at high voltage, pd1 to pd2 connection has no level shifter, what kind of design bugs and power related bugs can be seen? SystemVerilog SystemVerilog , UPF--power-aware , Low-Power--UPF , UPF , Advanced-Verification	0	1035	November 17, 2017
What type of RTL bugs can be caught using power verification? SystemVerilog SystemVerilog , UPF--power-aware , UPF	2	1648	October 9, 2017
Power Aware: Unable to understand the isolation signal name defined in the UPF file UVM UVM , UPF--power-aware	1	1136	December 22, 2015