Topics tagged UPF

Topic	Replies	Views	Activity
Best way to waive one signal mismatching isolation value versus reset value SystemVerilog Questa-Power-Aware-Simulator , UPF--power-aware , Low-Power--UPF , UPF , Low-Power-Verification , Questa-Power-Aware	0	32	February 13, 2025
Difference between UPF instrumentation and Instantiation SystemVerilog SystemVerilog , UPF--power-aware , Low-Power--UPF , UPF	1	594	October 21, 2021
We have two domain pd1 at low voltage and pd2 at high voltage, pd1 to pd2 connection has no level shifter, what kind of design bugs and power related bugs can be seen? SystemVerilog SystemVerilog , UPF--power-aware , Low-Power--UPF , UPF , Advanced-Verification	0	1118	November 17, 2017
What type of RTL bugs can be caught using power verification? SystemVerilog SystemVerilog , UPF--power-aware , UPF	2	1886	October 9, 2017
Does Questa support Power aware simulation with two different UPF files to be applied to different disign hierarchy UVM UVM , Questa-Power-Aware-Simulator , UPF	1	1264	September 12, 2016

Questa-Power-Aware-Simulator , UPF--power-aware , Low-Power--UPF , UPF , Low-Power-Verification , Questa-Power-Aware

0

32

February 13, 2025

Difference between UPF instrumentation and Instantiation

SystemVerilog , UPF--power-aware , Low-Power--UPF , UPF

1

594

October 21, 2021

SystemVerilog , UPF--power-aware , Low-Power--UPF , UPF , Advanced-Verification

0

1118

November 17, 2017

What type of RTL bugs can be caught using power verification?

SystemVerilog , UPF--power-aware , UPF

2

1886

October 9, 2017

UVM , Questa-Power-Aware-Simulator , UPF

1

1264

September 12, 2016