Topics tagged Low-Power--UPF

Topic	Replies	Views	Activity
Best way to waive one signal mismatching isolation value versus reset value SystemVerilog Questa-Power-Aware-Simulator , UPF--power-aware , Low-Power--UPF , UPF , Low-Power-Verification , Questa-Power-Aware	0	24	February 13, 2025
Low-power verification (UPF methodology) in non-power aware simulation tool UVM UVM , Low-Power--UPF	1	874	November 29, 2023
Difference between UPF instrumentation and Instantiation SystemVerilog SystemVerilog , UPF--power-aware , Low-Power--UPF , UPF	1	593	October 21, 2021
I would like to know how many ways we have to debug when anything goes wrong in UPF UVM UVM , UPF--power-aware , Low-Power--UPF	1	595	October 2, 2021
Is there something called power isolation cell and if yes whats the difference between Power isolation cell vs isolation cell UVM UVM , UPF--power-aware , Low-Power--UPF	2	1196	October 17, 2018
We have two domain pd1 at low voltage and pd2 at high voltage, pd1 to pd2 connection has no level shifter, what kind of design bugs and power related bugs can be seen? SystemVerilog SystemVerilog , UPF--power-aware , Low-Power--UPF , UPF , Advanced-Verification	0	1118	November 17, 2017
Working Example of UPF SystemVerilog SystemVerilog , Low-Power--UPF	4	3109	February 8, 2017
Web Seminar Notification: Advanced Verification for All: SV/UVM, UCIS, UPF Made Easy Announcements Announcements , UCIS , Web-Seminar , Verification-IP , SystemVerilog--UVM , Low-Power--UPF	0	1674	August 22, 2016