In low power verification, we typically deal with power-up and power-down sequences for power-gated IPs.
During the power-up sequence, the order I’ve often seen is:
Power ON → Reset → State Restore → Isolation Enable De-asserted → Clock Enable
However, I have a concern:
Without the clock being active, how are the restored values (from state retention logic) updated inside the IP?
Is this power-up sequence correct, or should the clock be enabled earlier in order to properly latch the restored values?