Low-power verification (UPF methodology) in non-power aware simulation tool


Currently I get a chance to verify the PMU (Power Management Unit) Block in Soc design.
I think this is an opportunity to develop low-power verification (UPF methodology) experience.
But I’m new for UPF methodology and I heard that this company is affordable to use the Power-Aware Simulator EDA Tool(Because the high cost of the EDA tool) and I found that some files are existing as “*.upf”.

From here, I’m wondering that whether Systemverilog or UVM can support low-power verification (UPF methodology) without such as PA-Tools and what things I need to do to get a low-power verification (UPF methodology) experience in this circumstance.

In reply to UVM_LOVE:

Low-power verification, particularly using UPF (Unified Power Format) methodology, is typically associated with specialized tools, such as power-aware simulators and power-aware debuggers. However, you can still perform some aspects of low-power verification using SystemVerilog and UVM even if you don’t have access to dedicated power-aware simulation tools.

Here are some general steps you can take to perform low-power verification using SystemVerilog and UVM:

Understand UPF:
Familiarize yourself with UPF (IEEE 1801) standard and its concepts. Understand how UPF is used to describe power intent in a design.
Manual Assertions:

Use SystemVerilog assertions (property, sequence, etc.) to manually model and verify power-related behaviors in your design.

Simulation Control:
Use SystemVerilog simulation control features to manage power modes and transitions in your design.

Custom Stimulus:
Develop custom stimulus to toggle power domains, create different power states, and observe the effects on the design.

Implement covergroups to track coverage related to power states and transitions.

Clock Gating:
If applicable, model and verify clock gating using SystemVerilog constructs.

Leakage Power Modeling:
If you have information about power consumption in different states, you can manually model leakage power in your testbenches.

UVM-based Verification:
Integrate low-power features into your UVM-based testbenches. This could involve extending UVM sequences and creating new UVM components to handle power-related transactions.

Keep in mind that while you can perform some aspects of low-power verification using SystemVerilog and UVM, the comprehensive verification of advanced low-power features often requires dedicated power-aware simulators. These tools can provide accurate power estimation, better modeling of power states, and efficient handling of complex power scenarios.

If the company has UPF files and mentions power-aware simulation tools, it’s worth checking if there are specific instructions or recommendations regarding low-power verification within their environment. Additionally, discuss with your team or supervisor to understand the expectations and limitations associated with low-power verification in your specific project and toolset.

Freelancer/verification engineer