With power verification we can see if the chip functions normally after being powered up, by observing its isolation cell output, retention cells. But all this are related to UPF,are there any RTL bugs that can be caught using power verification.
In reply to sgthoppa:
You have blocks that control the driving of isolation/retention/power down signals and orchestrate how the entire chip goes through power modes. If there are any bugs in the logic of these blocks you would find it in a UPF simulation. Also, I can imagine that you don’t want something like block A that is turned on trying to access block B that is turned off. If there is an RTL bug on SoC level that prevents block A from knowing that block B is currently turned off, because some status signal isn’t properly connected, then you would potentially find this with UPF.
Note that I’m not saying that UPF is the only way to find the aforementioned bugs.
Disclaimer: I don’t do SoC verification.
In reply to sgthoppa:
UPF describes part of the design that deals with active power management within an SoC.
This includes specifying abstract power distribution network, partitioning the design into power domains, specifying policies for isolation, level shifting etc and specifying RTL logic signals that control power switches, isolation cells and retention Flops.
The SoC RTL + UPF together forms the complete design. This complete perspective should be verified to ensure functional correctness. For example an RTL block within your SoC may be in a power domain that could be powered down. If this block is driving other RTL blocks in other power domains that could be ON at the same time, then it is necessary to isolate the signals that cross between these power domains. These isolated signals are clamped to a specific logic value so the upstream logic sees a valid logic value.
One then needs to verify that powering down a power domain does not cause other parts of the design (that are still ON) to behave incorrectly due to missing, or incorrect isolation specification
In addition, there is need to verify that the power down and power up sequences for each domain does in fact drive the logic within the domain into the desired power state (ON or OFF or even standby due to Low Vdd or Back bias)
Typically power aware verification is done at SoC level. However recent advances in UPF makes it possible to do functional verification early at the sub block level taking advantage of abstractions in UPF.
To learn more about functional verification of active power managed designs visit Power Aware Verification | Simulation-Based Techniques | Verification Academy