In reply to sgthoppa:
You have blocks that control the driving of isolation/retention/power down signals and orchestrate how the entire chip goes through power modes. If there are any bugs in the logic of these blocks you would find it in a UPF simulation. Also, I can imagine that you don’t want something like block A that is turned on trying to access block B that is turned off. If there is an RTL bug on SoC level that prevents block A from knowing that block B is currently turned off, because some status signal isn’t properly connected, then you would potentially find this with UPF.
Note that I’m not saying that UPF is the only way to find the aforementioned bugs.
Disclaimer: I don’t do SoC verification.