Given-a-32-bit-address-field-as-a-class-member

SystemVerilog ,  Given-a-32-bit-address-field-as-a-class-member ,  write-a-constraint-to-generate-a-random-value-such-that-it-always-has-10-bits-as-1-and-no-two-bits-next-to-each-other-should-be-1