Topics tagged SystemVerilog-Syntax

Topic	Replies	Views	Activity
String concatenation and/or ternary operator behaves weirdly wit $fwrite SystemVerilog SystemVerilog , SystemVerilog-Syntax , FWRITE	3	642	January 5, 2023
XOR in assertion property SystemVerilog SystemVerilog , assertion , SystemVerilog-Syntax , systemverilog-ASSERTION-bind	6	1464	June 15, 2022
Why I get the error: Uxexpected SystemVerilog keywork "package"? UVM UVM , SystemVerilog-Syntax , queues-systemverilog	1	3691	May 20, 2022
Hdl hierarchy alignment with some redundant character SystemVerilog SystemVerilog , SystemVerilog-Syntax	2	488	January 21, 2022
Raise Objection Syntax UVM UVM , objection-syntax , illegal-declaration , SystemVerilog-Syntax	6	4619	January 6, 2017

SystemVerilog , SystemVerilog-Syntax , FWRITE

3

642

January 5, 2023

XOR in assertion property

SystemVerilog , assertion , SystemVerilog-Syntax , systemverilog-ASSERTION-bind

6

1464

June 15, 2022

Why I get the error: Uxexpected SystemVerilog keywork "package"?

UVM , SystemVerilog-Syntax , queues-systemverilog

1

3691

May 20, 2022

Hdl hierarchy alignment with some redundant character

SystemVerilog , SystemVerilog-Syntax

2

488

January 21, 2022

Raise Objection Syntax

UVM , objection-syntax , illegal-declaration , SystemVerilog-Syntax

6

4619

January 6, 2017