Raise Objection Syntax

UVM
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1

Hi everyone,

I’m trying to build a dummy uvm enviroment. I’ve got an compilation error which I actually solved but I don’t know the reason . What I recognized is that i can not write anything before the create statement.

In the run_phase of my dummy test I want to raise an objection, create a sequence, start the sequence and drop the objection.

Below is run_phase method which can be compiled without errors.


task dummy_test::run_phase(uvm_phase phase);
  abc_sequence abc = abc_sequence::type_id::create("abc");
  phase.raise_objection (this, "dummy_test");
  abc.start(m_env.m_v_sequencer.abc_sequencer_t);
  #100ns;
  phase.drop_objection(this , "dummy_test");
endtask : run_phase

Below is run_phase method which can’t be compiled due to Illegal declaration error.
Error message;
dummy_test.sv(25): Illegal declaration after the statement near line ‘23’. Declarations must be precede statements. Look for stray semicolons.
Line 25 is the sequence start line
Line 23 is the raise objection line


task dummy_test::run_phase(uvm_phase phase);
  phase.raise_objection (this, "dummy_test");
  abc_sequence abc = abc_sequence::type_id::create("abc");
  abc.start(m_env.m_v_sequencer.abc_sequencer_t);
  #100ns;
  phase.drop_objection(this , "dummy_test");
endtask : run_phase

What am I missing and what shouldn’t I do ?

2

In reply to enbiya.h:

Hi,

in system verilog it is not allowed to declare variables after a command.

In verilog a task was defined like this:

task a();
reg i = 0;
begin
call_to_function();
endtask;

In system verilog it is allowed to leave the begin out but you still have to follow the
order.

I hope this helps bye

3

In reply to frodus:

In reply to enbiya.h:
Hi,
in system verilog it is not allowed to declare variables after a command.
In verilog a task was defined like this:
task a();
reg i = 0;
begin
call_to_function();
endtask;
In system verilog it is allowed to leave the begin out but you still have to follow the
order.
I hope this helps bye

Thank you.
By building the enviroment I was referring to the cookbook examples. In the Block Level Testbench example we can see the blow given run phase method in spi_test.


task spi_test::run_phase(uvm_phase phase);
  phase.raise_objection(this, "spi_test");
  check_regs_seq reset_test_seq = check_regs_seq::type_id::create("rest_test_seq");
  send_spi_char_seq spi_char_seq = send_spi_char_seq::type_id::create("spi_char_seq");

  reset_test_seq.start(m_env.m_v_sqr.apb);
  spi_char_seq.start(m_env.m_v_sqr.apb);
  #100ns;
  phase.drop_objection(this, "spi_test");
endtask: run_phase
4

In reply to enbiya.h:
That code snippit is not legal - within any procedural block of code, all declarations must precede any statements. If you can post a link to where you saw this, I can try to get it fixed,

5

In reply to dave_59:

In reply to enbiya.h:
That code snippit is not legal - within any procedural block of code, all declarations must precede any statements. If you can post a link to where you saw this, I can try to get it fixed,

Hi Dave,
I saw it on the example “Complete block level testbench example for a simple SPI DUT”. Below is the download link for the example and the path for the code snippet.

Block Level Testbench - Complete block level testbench example for a simple SPI DUT.
Download link block level testbench example

…\tb_build\block_level_tbs\spi_tb\test\spi_test.svh Line:50

6

In reply to enbiya.h:

Hi,
If you only requirement is to create the sequence after raising an objection, you can spilt the declaration and creation of the sequence.
For eg.
task dummy_test::run_phase(uvm_phase phase);
abc_sequence abc; ==================================> Sequence declared
phase.raise_objection (this, “dummy_test”);
abc = abc_sequence::type_id::create(“abc”); =========> Sequence created
abc.start(m_env.m_v_sequencer.abc_sequencer_t);
#100ns;
phase.drop_objection(this , “dummy_test”);
endtask : run_phase

Hope this helps.

7

In reply to enbiya.h:

Hi,
If your only requirement is to create the sequence after raising an objection, you can spilt the declaration and creation of the sequence.
For eg.
task dummy_test::run_phase(uvm_phase phase);
abc_sequence abc; ==================================> Sequence declared
phase.raise_objection (this, “dummy_test”);
abc = abc_sequence::type_id::create(“abc”); =========> Sequence created
abc.start(m_env.m_v_sequencer.abc_sequencer_t);
#100ns;
phase.drop_objection(this , “dummy_test”);
endtask : run_phase

Hope this helps.