Raise Objection Syntax

UVM
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3

In reply to frodus:

In reply to enbiya.h:
Hi,
in system verilog it is not allowed to declare variables after a command.
In verilog a task was defined like this:
task a();
reg i = 0;
begin
call_to_function();
endtask;
In system verilog it is allowed to leave the begin out but you still have to follow the
order.
I hope this helps bye

Thank you.
By building the enviroment I was referring to the cookbook examples. In the Block Level Testbench example we can see the blow given run phase method in spi_test.


task spi_test::run_phase(uvm_phase phase);
  phase.raise_objection(this, "spi_test");
  check_regs_seq reset_test_seq = check_regs_seq::type_id::create("rest_test_seq");
  send_spi_char_seq spi_char_seq = send_spi_char_seq::type_id::create("spi_char_seq");

  reset_test_seq.start(m_env.m_v_sqr.apb);
  spi_char_seq.start(m_env.m_v_sqr.apb);
  #100ns;
  phase.drop_objection(this, "spi_test");
endtask: run_phase