Why I get the error: Uxexpected SystemVerilog keywork "package"?

UVM
, ,
1

Hi!

I am trying to compile my UVM code, when I get the error Uxexpected SystemVerilog keywork “package”.

I was looking for a missing semicolon or some syntax error in my code, but I could not find anything.

I attach my code and the error obtained. The code is very extensive, so I attach the testbench, include and package files. Also the .do and a extract of the transcript with the error obtanied. Thanks!

 `timescale 1ps/1ps
  `timescale 1ps/1ps
  

  `include "uvm_macros.svh"
  `include "../testbench/includes.sv"
  import uvm_pkg::*;


  //class: testbench
  module testbench;
    import define_pkg::*;
    import test_pkg::*;

    int log_file_asserts_h;

    // Variable: log_file_h
    // Handler to log file.
    int log_file_h;

    // Variable: test_name
    // Test name string to compose log file name.
    string test_name;

    // Variable: msg
    // Auxiliary string.
    string msg;

    // Variable: current_step
    // Step number printed in reports.
    int current_step = 1;

    wire [3:0]  dut_to_flash_cle;
    wire [3:0]  dut_to_flash_ale;
    wire [3:0]  dut_to_flash_nwe;
    wire        dut_to_flash_nwp;
    wire [7:0]  dut_to_flash_nce_0_1;
    wire [7:0]  dut_to_flash_nce_2_3;
    wire [3:0]  dut_to_flash_nre;
    wire [15:0] dut_to_flash_data_0_1;
    wire [15:0] dut_to_flash_data_2_3;
    wire [7:0]  dut_to_flash_rnb;
    wire [7:0]  dut_to_flash_chan_sel;


    wire [17:0] dut_to_sram_address;
    wire [15:0] dut_to_sram_data;
    wire        dut_to_sram_ce0;
    wire        dut_to_sram_ce1;
    wire        dut_to_sram_oe;
    wire        dut_to_sram_we;

    wire dut_to_hk_spw_dout_o;
    wire dut_to_hk_spw_sout_o;
    wire dut_to_hk_spw_din_i;
    wire dut_to_hk_spw_sin_i;

    wire dut_to_sci_spw_dout_o;
    wire dut_to_sci_spw_sout_o;
    wire dut_to_sci_spw_din_i;
    wire dut_to_sci_spw_sin_i;

    wire dut_to_out_spw_dout_o;
    wire dut_to_out_spw_sout_o;
    wire dut_to_out_spw_din_i;
    wire dut_to_out_spw_sin_i;

    wire dut_to_hk_spw_dout_no;
    wire dut_to_hk_spw_sout_no;
    wire dut_to_sci_spw_dout_no;
    wire dut_to_sci_spw_sout_no;
    wire dut_to_out_spw_dout_no;
    wire dut_to_out_spw_sout_no;

    wire [16:0] dut_to_mram_address_o;
    wire [7:0]  dut_to_mram_data_io;
    wire        dut_to_mram_ce0_no;
    wire        dut_to_mram_ce1_no;
    wire        dut_to_mram_ce2_no;
    wire        dut_to_mram_ce3_no;
    wire        dut_to_mram_oe_no;
    wire        dut_to_mram_we_no;

    clock_reset_intf vintf_clock_reset();

    dh_fpga_intf vintf_dh_fpga();

    flash_intf vintf_flash();

    mram_intf vintf_mram();

    sram_intf vintf_sram();

    hk_spw_intf vintf_hk_spw();

    sci_spw_intf vintf_sci_spw();

    out_spw_intf vintf_out_spw();

    assign dut_to_flash_cle = m_flash_intf.flash_cle_o;
    assign dut_to_flash_ale = m_flash_intf.flash_ale_o;
    assign dut_to_flash_nwe = m_flash_intf.flash_nwe_o;
    assign dut_to_flash_nwp = m_flash_intf.flash_nwp_o;
    assign dut_to_flash_nce_0_1 = m_flash_intf.flash_nce_0_1_o;
    assign dut_to_flash_nce_2_3 = m_flash_intf.flash_nce_2_3_o;
    assign dut_to_flash_nre = m_flash_intf.flash_nre_o;
    assign dut_to_flash_data_0_1 = m_flash_intf.flash_data_0_1_io;
    assign dut_to_flash_data_2_3 = m_flash_intf.flash_data_2_3_io;
    assign dut_to_flash_rnb = m_flash_intf.flash_rnb_i;
    assign dut_to_flash_chan_sel = m_flash_intf.flash_chan_sel_o;

    assign dut_to_sram_address = m_sram_intf.sram_address;
    assign dut_to_sram_data = m_sram_intf.sram_data;
    assign dut_to_sram_ce0 = m_sram_intf.sram_ce0;
    assign dut_to_sram_ce1 = m_sram_intf.sram_ce1;
    assign dut_to_sram_oe = m_sram_intf.sram_oe;
    assign dut_to_sram_we = m_sram_intf.sram_we;

    assign dut_to_hk_spw_dout_o = m_hk_spw_intf.hk_spw_dout_o; 
    assign dut_to_hk_spw_sout_o = m_hk_spw_intf.hk_spw_sout_o; 
    assign dut_to_hk_spw_din_i = m_hk_spw_intf.hk_spw_din_i; 
    assign dut_to_hk_spw_sin_i = m_hk_spw_intf.hk_spw_sin_i; 

    assign dut_to_sci_spw_dout_o = m_sci_spw_intf.sci_spw_dout_o; 
    assign dut_to_sci_spw_sout_o = m_sci_spw_intf.sci_spw_sout_o; 
    assign dut_to_sci_spw_din_i = m_sci_spw_intf.sci_spw_din_i; 
    assign dut_to_sci_spw_sin_i = m_sci_spw_intf.sci_spw_sin_i; 

    assign dut_to_out_spw_dout_o = m_out_spw_intf.out_spw_dout_o; 
    assign dut_to_out_spw_sout_o = m_out_spw_intf.out_spw_sout_o; 
    assign dut_to_out_spw_din_i = m_out_spw_intf.out_spw_din_i; 
    assign dut_to_out_spw_sin_i = m_out_spw_intf.out_spw_sin_i; 

    assign dut_to_mram_address_o = m_mram_intf.mram_address_o;
    assign dut_to_mram_data_io = m_mram_intf.mram_data_io;
    assign dut_to_mram_ce0_no = m_mram_intf.mram_ce0_no;
    assign dut_to_mram_ce1_no = m_mram_intf.mram_ce1_no;
    assign dut_to_mram_ce2_no = m_mram_intf.mram_ce2_no;
    assign dut_to_mram_ce3_no = m_mram_intf.mram_ce3_no;
    assign dut_to_mram_oe_no = m_mram_intf.mram_oe_no;
    assign dut_to_mram_we_no = m_mram_intf.mram_we_no;

    top_wrapper u_top_wrapper(
      vintf_clock_reset,
      vintf_dh_fpga,
      vintf_flash,
      vintf_mram,
      vintf_sram,
      vintf_hk_spw,
      vintf_sci_spw,
      vintf_out_spw
    );


  //   flash_bank u_flash_bank(
  //     .flash_cle_i        (dut_to_flash_cle),           
  //     .flash_ale_i        (dut_to_flash_ale),           
  //     .flash_nwe_i        (dut_to_flash_nwe),           
  //     .flash_nwp_i        (dut_to_flash_nwp),           
  //     .flash_nce_2_3_i    (dut_to_flash_nce_2_3),       
  //     .flash_nce_0_1_i    (dut_to_flash_nce_0_1),       
  //     .flash_nre_i        (dut_to_flash_nre),           
  //     .flash_data_2_3_io  (dut_to_flash_data_2_3),     
  //     .flash_data_0_1_io  (dut_to_flash_data_0_1),     
  //     .flash_rnb_o        (dut_to_flash_rnb),           
  //     .flash_dir_i        (1'b0),           
  //     .chan_sel_i         (dut_to_flash_chan_sel)          
  //   );

  // spw_link_tb u_hk_spw_link(
  //   .devrst_no(),           
  //   .srst_o(),              
  //   .spw_tb_dout_p_o(dut_to_hk_spw_dout_o),     
  //   .spw_tb_dout_n_o(),     
  //   .spw_tb_sout_p_o(dut_to_hk_spw_sout_o),     
  //   .spw_tb_sout_n_o(),     
  //   .spw_tb_din_p_i(dut_to_hk_spw_din_i),      
  //   .spw_tb_din_n_i(~dut_to_hk_spw_din_i),      
  //   .spw_tb_sin_p_i(dut_to_hk_spw_sin_i),      
  //   .spw_tb_sin_n_i(~dut_to_hk_spw_sin_i)      
  // );

  // spw_sci_link u_sci_spw_link(
  //   .devrst_no(),           
  //   .srst_o(),              
  //   .spw_tb_dout_p_o(dut_to_sci_spw_dout_o),     
  //   .spw_tb_dout_n_o(dut_to_sci_spw_dout_no),     
  //   .spw_tb_sout_p_o(dut_to_sci_spw_sout_o),     
  //   .spw_tb_sout_n_o(dut_to_sci_spw_sout_no),     
  //   .spw_tb_din_p_i(dut_to_sci_spw_din_i),      
  //   .spw_tb_din_n_i(~dut_to_sci_spw_din_i),      
  //   .spw_tb_sin_p_i(dut_to_sci_spw_sin_i),      
  //   .spw_tb_sin_n_i(~dut_to_sci_spw_sin_i)      
  // );

  // spw_out_link u_out_spw_link(
  //   .devrst_no(),           
  //   .srst_o(),              
  //   .spw_tb_dout_p_o(dut_to_out_spw_dout_o),     
  //   .spw_tb_dout_n_o(dut_to_out_spw_dout_no),     
  //   .spw_tb_sout_p_o(dut_to_out_spw_sout_o),     
  //   .spw_tb_sout_n_o(dut_to_out_spw_sout_no),     
  //   .spw_tb_din_p_i(dut_to_out_spw_din_i),      
  //   .spw_tb_din_n_i(~dut_to_out_spw_din_i),      
  //   .spw_tb_sin_p_i(dut_to_out_spw_sin_i),      
  //   .spw_tb_sin_n_i(~dut_to_out_spw_sin_i)      
  // );

  // CY7C1061GN_10 u_sram(
  //     .A(dut_to_sram_address),
  //     .CE_b0(dut_to_sram_ce0),
  //     .CE_b1(dut_to_sram_ce1),
  //     .OE_b(dut_to_sram_oe),
  //     .WE_b(dut_to_sram_we),
  //     .DQ(dut_to_sram_data)
  // );

  // MRAM_CY7C1061GN_10 u_mram(
  //     .CE_b0(dut_to_mram_ce0_no),
  //     .CE_b1(dut_to_mram_ce1_no),
  //     .CE_b2(dut_to_mram_ce2_no),
  //     .CE_b3(dut_to_mram_ce3_no),
  //     .WE_b(dut_to_mram_we_no),
  //     .OE_b(dut_to_mram_oe_no),
  //     .A(dut_to_mram_address_o),
  //     .DQ(dut_to_mram_data_io)
  // );


    initial begin

      // Configure some simulation options.
      uvm_top.enable_print_topology = 1;
      uvm_top.finish_on_completion  = 0;

    
      //Get test name from CLI.
      void'($value$plusargs("UVM_TESTNAME=%s",test_name));
      msg={"./log_files/",test_name,".log"};

      //Open file to save log messages according to selected test.
      log_file_h = $fopen(msg);
      if(!log_file_h) begin
        `uvm_fatal("Testbench", "Unable to open log file!!!");
      end

      //Set default verbosity level for all TB components.
      uvm_top.set_report_verbosity_level_hier(UVM_LOW);

      msg=$sformatf("#------------------Running test: %s----------------------#",test_name);
      $fdisplay(log_file_h,"#-------------------------------------------------------------#");
      $fdisplay(log_file_h,msg);
      $display(msg);
      $fdisplay(log_file_h,"#-------------------------------------------------------------#\n");
      
      //Set the agents' interfaces.
      uvm_config_db #(virtual clock_reset_intf)::set(null, "uvm_test_top", "m_clock_reset_agent_vif", vintf_clock_reset);

      uvm_config_db #(virtual dh_fpga_intf)::set(null, "uvm_test_top", "m_dh_fpga_agent_vif", vintf_dh_fpga);

      uvm_config_db #(virtual flash_intf)::set(null, "uvm_test_top", "m_flash_agent_vif", vintf_flash);

      uvm_config_db #(virtual mram_intf)::set(null, "uvm_test_top", "m_mram_agent_vif", vintf_mram);

      uvm_config_db #(virtual sram_intf)::set(null, "uvm_test_top", "m_sram_agent_vif", vintf_sram);

      uvm_config_db #(virtual hk_spw_intf)::set(null, "uvm_test_top", "m_hk_spw_agent_vif", vintf_hk_spw);

      uvm_config_db #(virtual sci_spw_intf)::set(null, "uvm_test_top", "m_sci_spw_agent_vif", vintf_sci_spw);

      uvm_config_db #(virtual out_spw_intf)::set(null, "uvm_test_top", "m_out_spw_agent_vif", vintf_out_spw);
      
      //Set log file handler.
      uvm_config_db #(int)::set(null, "*", "m_log_file_h", log_file_h);
      
      // Set current step for log file.
      uvm_config_db #(int)::set(null, "*", "m_curr_step", current_step);
      

      //Run the specified test case by UVM_TEST command. 
      run_test();

      //Close log file.
      $fclose(log_file_h);


    end
   
  endmodule: testbench

System Verilog

 
 `include "../tests/define_pkg.sv" 
  
 `include "../agents/clock_reset_agent/sequence_lib/clock_reset_seq_pkg.sv"
 `include "../agents/clock_reset_agent/clock_reset_agent_pkg.sv"
 `include "../agents/clock_reset_agent/clock_reset_intf.sv"
  
  `include "../agents/dh_fpga_agent/sequence_lib/dh_fpga_seq_pkg.sv"
  `include "../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv"
  `include "../agents/dh_fpga_agent/dh_fpga_intf.sv"

  `include "../agents/flash_agent/sequence_lib/flash_seq_pkg.sv"
  `include "../agents/flash_agent/flash_agent_pkg.sv"
  `include "../agents/flash_agent/flash_intf.sv"

  `include "../agents/hk_spw_agent/sequence_lib/hk_spw_seq_pkg.sv"
  `include "../agents/hk_spw_agent/hk_spw_agent_pkg.sv"
  `include "../agents/hk_spw_agent/hk_spw_intf.sv"

  `include "../agents/mram_agent/sequence_lib/mram_seq_pkg.sv"
  `include "../agents/mram_agent/mram_agent_pkg.sv"
  `include "../agents/mram_agent/mram_intf.sv"
 
  `include "../agents/out_spw_agent/sequence_lib/out_spw_seq_pkg.sv"
  `include "../agents/out_spw_agent/out_spw_agent_pkg.sv"
  `include "../agents/out_spw_agent/out_spw_intf.sv"

  `include "../agents/sci_spw_agent/sequence_lib/sci_spw_seq_pkg.sv"
  `include "../agents/sci_spw_agent/sci_spw_agent_pkg.sv"
  `include "../agents/sci_spw_agent/sci_spw_intf.sv"

  `include "../agents/sram_agent/sequence_lib/sram_seq_pkg.sv"
  `include "../agents/sram_agent/sram_agent_pkg.sv"
  `include "../agents/sram_agent/sram_intf.sv"

  `include "../register_model/top_regs_pkg.sv"

  `include "../environment/environment_pkg.sv"
    
  `include "../sequences/test_seq_pkg.sv"

  `include "../tests/test_pkg.sv"

ifndef DEFINE_PKG__SV define DEFINE_PKG__SV

// Package: define_pkg
// Package for general constants.
package define_pkg;

// variable: CLK_PERIOD_NS
// Clock period in ns.
//localparam int CLK_PERIOD_NS = 20;

// // variable: ACCESS_SRAM_CYCLES
// // SRAM time access in clock cycles.
// localparam int ACCESS_SRAM_CYCLES = 1;

// // variable: ACCESS_MRAM_CYCLES
// // MRAM time access in clock cycles.
// localparam int ACCESS_MRAM_CYCLES = 0;

// // variable: N_CYCLES_SOFT_RESET
// // Number of clock cycles for soft reset active.
// localparam int N_CYCLES_SOFT_RESET = 10;

// // variable: N_CYCLES_HARD_RESET
// // Number of clock cycles for hard reset active.
// localparam int N_CYCLES_HARD_RESET = 10;

endpackage : define_pkg

`endif

.do file****

Set paths and env

set MAIN_PATH [pwd]
set WORK_LIB_DIR ./work
set WORK_LIB_NAME work
##set RTG4_LIB_DIR $MAIN_PATH/12.4_Questasim_10.7c_rtg4
##set RTG4_LIB_NAME RTG4

set TOOL C:/questasim64_10.7c/verilog_src/uvm-1.1d

set UVM_TESTRUN $1

Quit previous simulation

quit -sim

Clear transcript windows

.main clear

Close previous transcript file

transcript file “”

puts [string repeat “-” 72]
echo $MAIN_PATH
puts [string repeat “-” 72]

if [file exists work] {vdel -all}
if [file exists RTGA] {vdel -all}

vlib $WORK_LIB_NAME
vmap $WORK_LIB_NAME $WORK_LIB_DIR

#vlib $RTG4_LIB_NAME
#vmap $RTG4_LIB_NAME $RTG4_LIB_DIR

vcom -work work ../rtl/mm_top.vhd

vlog -coveropt 3 +cover -work work -f simTest.f +define+UVM_NO_DPI +define+UVM_REG_DATA_WIDTH=32

vsim +UVM_TESTNAME=UVM_TESTRUN -coverage -t 1ps -vopt work.testbench -c -do "coverage save -onexit -directive -codeAll coverage2.ucdb; transcript file {UVM_TESTRUN}_log.txt; add wave -position insertpoint sim:/testbench/u_top_wrapper/u_dS3r_top/*; run -all"
vsim +UVM_TESTNAME=UVM_TESTRUN -coverage -t 1ps -vopt work.testbench -c -do "coverage save -onexit -directive -codeAll coverage2.ucdb; transcript file {UVM_TESTRUN}_log.txt;"
vsim -coverage -t 1ps -vopt work.testbench -c -do “coverage save -onexit -directive -codeAll coverage2.ucdb;”

source wave_ds3r_top.do

run -all

Transcript file__

– Loading entity spw_input_top

– Loading entity buff_ctrl_top

– Loading entity amba_uart_bridge_50000000_115200

– Loading entity mram_ctrl_top

End time: 13:37:11 on May 20,2022, Elapsed time: 0:00:40

Errors: 0, Warnings: 0

QuestaSim-64 vlog 10.7c Compiler 2018.08 Aug 18 2018

Start time: 13:37:12 on May 20,2022

vlog -reportprogress 300 -coveropt 3 “+cover” -work work -f simTest.f “+define+UVM_NO_DPI” “+define+UVM_REG_DATA_WIDTH=32”

– Compiling package uvm_pkg (uvm-1.1d Built-in)

– Compiling module top_wrapper

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(2)

** at ../sim/testbench/../tests/define_pkg.sv(6): near “package”: syntax error, unexpected “SystemVerilog keyword ‘package’”.

– Importing package uvm_pkg (uvm-1.1d Built-in)

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(4)

** at ../sim/testbench/../agents/clock_reset_agent/sequence_lib/clock_reset_seq_pkg.sv(18): near “endpackage”: syntax error, unexpected “SystemVerilog keyword ‘endpackage’”.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(5)

** at ../sim/testbench/../agents/clock_reset_agent/clock_reset_agent_pkg.sv(11): (vlog-13006) Could not find the package (clock_reset_seq_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(5)

** while parsing file included at ../sim/testbench/../agents/clock_reset_agent/clock_reset_agent_pkg.sv(16)

** at ..\sim\testbench..\agents\clock_reset_agent\clock_reset_driver.sv(4): (vlog-13006) Could not find the package (define_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(5)

** while parsing file included at ../sim/testbench/../agents/clock_reset_agent/clock_reset_agent_pkg.sv(16)

** at ..\sim\testbench..\agents\clock_reset_agent\clock_reset_driver.sv(104): (vlog-2730) Undefined variable: ‘N_CYCLES_HARD_RESET’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(5)

** while parsing file included at ../sim/testbench/../agents/clock_reset_agent/clock_reset_agent_pkg.sv(16)

** at ..\sim\testbench..\agents\clock_reset_agent\clock_reset_driver.sv(104): (vlog-2730) Undefined variable: ‘CLK_PERIOD_NS’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(5)

** while parsing file included at ../sim/testbench/../agents/clock_reset_agent/clock_reset_agent_pkg.sv(16)

** at ..\sim\testbench..\agents\clock_reset_agent\clock_reset_driver.sv(126): (vlog-2730) Undefined variable: ‘CLK_PERIOD_NS’.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(5)

** at ../sim/testbench/../agents/clock_reset_agent/clock_reset_agent_pkg.sv(21): near “endpackage”: syntax error, unexpected “SystemVerilog keyword ‘endpackage’”.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(6)

** at ../sim/testbench/../agents/clock_reset_agent/clock_reset_intf.sv(18): near “endinterface”: syntax error, unexpected “SystemVerilog keyword ‘endinterface’”.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(8)

** at ../sim/testbench/../agents/dh_fpga_agent/sequence_lib/dh_fpga_seq_pkg.sv(18): near “endpackage”: syntax error, unexpected “SystemVerilog keyword ‘endpackage’”.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(11): (vlog-13006) Could not find the package (dh_fpga_seq_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(16)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_driver.sv(4): (vlog-13006) Could not find the package (define_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(16)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_driver.sv(91): (vlog-2730) Undefined variable: ‘N_CYCLES_SOFT_RESET’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(16)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_driver.sv(91): (vlog-2730) Undefined variable: ‘CLK_PERIOD_NS’.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(16)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_driver.sv(105): near “end”: syntax error, unexpected end.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(17)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(9)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(9): (vlog-2730) Undefined variable: ‘dh_fpga_monitor’.

** Warning: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(17)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(9)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(9): (vlog-2953) Incorrect usage of keyword ‘static’.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(17)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(9)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(9): near “function”: syntax error, unexpected function, expecting IDENTIFIER or TYPE_IDENTIFIER or NETTYPE_IDENTIFIER.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(17)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(9)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(9): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(17)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(9)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(9): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(17)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(24): Illegal declaration after the statement near line ‘13’. Declarations must precede statements. Look for stray semicolons.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(17)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(33): (vlog-2164) Class or package ‘dh_fpga_monitor’ not found.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(17)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(34): ‘super.new()’ call can be made only from within a class constructor.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(17)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(35): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(17)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(39): (vlog-2164) Class or package ‘dh_fpga_monitor’ not found.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(17)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(44): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(17)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(49): (vlog-2164) Class or package ‘dh_fpga_monitor’ not found.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(17)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(54): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(17)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(62): (vlog-2164) Class or package ‘dh_fpga_monitor’ not found.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(17)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(76): Illegal declaration after the statement near line ‘62’. Declarations must precede statements. Look for stray semicolons.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(17)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(115): near “end”: syntax error, unexpected end.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(18)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_sequencer.sv(9)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_sequencer.sv(9): (vlog-2730) Undefined variable: ‘dh_fpga_sequencer’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(18)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_sequencer.sv(9)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_sequencer.sv(9): Typedef ‘type_id’ multiply defined.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(18)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_sequencer.sv(9)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_sequencer.sv(9): ‘get_type’ already exists; must not be redefined as a function.

** Warning: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(18)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_sequencer.sv(9)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_sequencer.sv(9): (vlog-2953) Incorrect usage of keyword ‘static’.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(18)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_sequencer.sv(9)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_sequencer.sv(9): near “function”: syntax error, unexpected function, expecting IDENTIFIER or TYPE_IDENTIFIER or NETTYPE_IDENTIFIER.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(18)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_sequencer.sv(9)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_sequencer.sv(9): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(18)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_sequencer.sv(9)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_sequencer.sv(9): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(18)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_sequencer.sv(17): (vlog-2164) Class or package ‘dh_fpga_sequencer’ not found.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(18)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_sequencer.sv(18): ‘super.new()’ call can be made only from within a class constructor.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(18)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_sequencer.sv(19): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(10)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(10): (vlog-2730) Undefined variable: ‘dh_fpga_agent’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(10)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(10): Typedef ‘type_id’ multiply defined.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(10)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(10): ‘get_type’ already exists; must not be redefined as a function.

** Warning: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(10)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(10): (vlog-2953) Incorrect usage of keyword ‘static’.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(10)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(10): near “function”: syntax error, unexpected function, expecting IDENTIFIER or TYPE_IDENTIFIER or NETTYPE_IDENTIFIER.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(10)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(10): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** while parsing macro expansion: ‘uvm_component_utils’ starting at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(10)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(10): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error (suppressible): ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_monitor.sv(21): (vlog-2388) ‘monitor_to_scoreboard_aport’ already declared in this scope (run_phase).

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(22): Illegal declaration after the statement near line ‘14’. Declarations must precede statements. Look for stray semicolons.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(30): Illegal declaration after the statement near line ‘22’. Declarations must precede statements. Look for stray semicolons.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(40): (vlog-2164) Class or package ‘dh_fpga_agent’ not found.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(41): ‘super.new()’ call can be made only from within a class constructor.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(42): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(47): (vlog-2164) Class or package ‘dh_fpga_agent’ not found.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(61): (vlog-2730) Undefined variable: ‘m_sequencer’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(61): (vlog-2164) Class or package ‘dh_fpga_sequencer’ not found.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(61): near “::”: syntax error, unexpected ::, expecting ‘;’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(69): (vlog-2730) Undefined variable: ‘m_monitor’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(69): (vlog-2164) Class or package ‘dh_fpga_monitor’ not found.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(69): near “::”: syntax error, unexpected ::, expecting ‘;’.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(76): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(81): (vlog-2164) Class or package ‘dh_fpga_agent’ not found.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(9)

** while parsing file included at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_agent_pkg.sv(19)

** at ..\sim\testbench..\agents\dh_fpga_agent\dh_fpga_agent.sv(93): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(10)

** at ../sim/testbench/../agents/dh_fpga_agent/dh_fpga_intf.sv(19): Illegal declaration after the statement near line ‘9’. Declarations must precede statements. Look for stray semicolons.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(7): Illegal declaration after the statement near line ‘7’. Declarations must precede statements. Look for stray semicolons.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9): (vlog-2730) Undefined variable: ‘flash_seq_item’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9): Typedef ‘type_id’ multiply defined.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9): ‘get_type’ already exists; must not be redefined as a function.

** Warning: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9): (vlog-2953) Incorrect usage of keyword ‘static’.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9): near “function”: syntax error, unexpected function, expecting IDENTIFIER or TYPE_IDENTIFIER or NETTYPE_IDENTIFIER.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9): near “;”: syntax error, unexpected ‘;’, expecting ‘(’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9): (vlog-2730) Undefined variable: ‘tmp’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9): (vlog-2730) Undefined variable: ‘name’.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9): near “;”: syntax error, unexpected ‘;’, expecting ‘(’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9): Illegal declaration after the statement near line ‘9’. Declarations must precede statements. Look for stray semicolons.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9): (vlog-2730) Undefined variable: ‘tmp_data__’.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(9): near “end”: syntax error, unexpected end.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(25): Illegal declaration after the statement near line ‘11’. Declarations must precede statements. Look for stray semicolons.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(34): (vlog-2164) Class or package ‘flash_seq_item’ not found.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(35): ‘super.new()’ call can be made only from within a class constructor.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(36): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(40): (vlog-2164) Class or package ‘flash_seq_item’ not found.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(41): near “;”: syntax error, unexpected ‘;’, expecting ‘(’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(48): (vlog-2730) Undefined variable: ‘addr’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(49): (vlog-2730) Undefined variable: ‘wdata’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(50): (vlog-2730) Undefined variable: ‘en_write_n’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(51): (vlog-2730) Undefined variable: ‘en_cs_n’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(52): (vlog-2730) Undefined variable: ‘rdata’.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(54): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(58): (vlog-2164) Class or package ‘flash_seq_item’ not found.

Break key hit

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(61): Illegal declaration after the statement near line ‘58’. Declarations must precede statements. Look for stray semicolons.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(67): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(71): (vlog-2164) Class or package ‘flash_seq_item’ not found.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_seq_item.sv(73): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14): (vlog-2730) Undefined variable: ‘flash_base_seq’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14): Typedef ‘type_id’ multiply defined.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14): ‘get_type’ already exists; must not be redefined as a function.

** Warning: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14): (vlog-2953) Incorrect usage of keyword ‘static’.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14): near “function”: syntax error, unexpected function, expecting IDENTIFIER or TYPE_IDENTIFIER or NETTYPE_IDENTIFIER.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14): near “;”: syntax error, unexpected ‘;’, expecting ‘(’.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14): near “;”: syntax error, unexpected ‘;’, expecting ‘(’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14): Typedef ‘local_type_’ multiply defined.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14): Illegal declaration after the statement near line ‘14’. Declarations must precede statements. Look for stray semicolons.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** while parsing macro expansion: ‘uvm_object_utils’ starting at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(14): near “end”: syntax error, unexpected end.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(30): (vlog-2164) Class or package ‘flash_base_seq’ not found.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(31): ‘super.new()’ call can be made only from within a class constructor.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(32): near “endfunction”: syntax error, unexpected endfunction, expecting endtask.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(39): (vlog-2164) Class or package ‘flash_base_seq’ not found.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(43): near “;”: syntax error, unexpected ‘;’, expecting ‘(’.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(47): near “;”: syntax error, unexpected ‘;’, expecting ‘(’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(57): Illegal declaration after the statement near line ‘47’. Declarations must precede statements. Look for stray semicolons.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(57): (vlog-2164) Class or package ‘flash_seq_item’ not found.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(58): (vlog-2730) Undefined variable: ‘rsq_item’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(58): (vlog-2164) Class or package ‘flash_seq_item’ not found.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(58): near “::”: syntax error, unexpected ::, expecting ‘;’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(78): (vlog-2730) Undefined variable: ‘memory’.

** Error: ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** while parsing file included at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(15)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(81): (vlog-2730) Undefined variable: ‘req_item’.

** Error (suppressible): ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** at ..\sim\testbench..\agents\flash_agent\sequence_lib\flash_base_seq.sv(91): (vlog-13163) End label ‘body’ does not match task name on line 55.

** Error: (vlog-13069) ** while parsing file included at ../sim/testbench/testbench.sv(5)

** while parsing file included at ../sim/testbench/../testbench/includes.sv(12)

** at ../sim/testbench/../agents/flash_agent/sequence_lib/flash_seq_pkg.sv(17): near “endpackage”: syntax error, unexpected “SystemVerilog keyword ‘endpackage’”.

SIGSEGV: segmentation violation

** Error: C:/questasim64_10.7c/win64/vlog failed.

Error in macro ./simTest.do line 36

C:/questasim64_10.7c/win64/vlog failed.

while executing

“vlog -coveropt 3 +cover -work work -f simTest.f +define+UVM_NO_DPI +define+UVM_REG_DATA_WIDTH=32”

2

In reply to kevinvig7:
An error message like this about a top-level keyword like 'package` usually means you are trying to compile a package inside another package, or forgot an endpackage or endmodule, or something like that.